1 /**************************************************************************//**
3 * @brief CMSIS Cortex-M Core Instruction Access Header File
9 ******************************************************************************/
10 /* Copyright (c) 2009 - 2013 ARM LIMITED
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
38 #ifndef __CORE_CMINSTR_H
39 #define __CORE_CMINSTR_H
42 /* ########################## Core Instruction Access ######################### */
43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
44 Access to dedicated instructions
48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
49 /* ARM armcc specific functions */
51 #if (__ARMCC_VERSION < 400677)
52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
56 /** \brief No Operation
58 No Operation does nothing. This instruction can be used for code alignment purposes.
63 /** \brief Wait For Interrupt
65 Wait For Interrupt is a hint instruction that suspends execution
66 until one of a number of events occurs.
71 /** \brief Wait For Event
73 Wait For Event is a hint instruction that permits the processor to enter
74 a low-power state until one of a number of events occurs.
81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
86 /** \brief Instruction Synchronization Barrier
88 Instruction Synchronization Barrier flushes the pipeline in the processor,
89 so that all instructions following the ISB are fetched from cache or
90 memory, after the instruction has been completed.
92 #define __ISB() __isb(0xF)
95 /** \brief Data Synchronization Barrier
97 This function acts as a special kind of Data Memory Barrier.
98 It completes when all explicit memory accesses before this instruction complete.
100 #define __DSB() __dsb(0xF)
103 /** \brief Data Memory Barrier
105 This function ensures the apparent order of the explicit memory operations before
106 and after the instruction, without ensuring their completion.
108 #define __DMB() __dmb(0xF)
111 /** \brief Reverse byte order (32 bit)
113 This function reverses the byte order in integer value.
115 \param [in] value Value to reverse
116 \return Reversed value
121 /** \brief Reverse byte order (16 bit)
123 This function reverses the byte order in two unsigned short values.
125 \param [in] value Value to reverse
126 \return Reversed value
128 #ifndef __NO_EMBEDDED_ASM
129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
136 /** \brief Reverse byte order in signed short value
138 This function reverses the byte order in a signed short value with sign extension to integer.
140 \param [in] value Value to reverse
141 \return Reversed value
143 #ifndef __NO_EMBEDDED_ASM
144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
152 /** \brief Rotate Right in unsigned value (32 bit)
154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
156 \param [in] value Value to rotate
157 \param [in] value Number of Bits to rotate
158 \return Rotated value
163 /** \brief Breakpoint
165 This function causes the processor to enter Debug state.
166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
168 \param [in] value is ignored by the processor.
169 If required, a debugger can use it to store additional information about the breakpoint.
171 #define __BKPT(value) __breakpoint(value)
174 #if (__CORTEX_M >= 0x03)
176 /** \brief Reverse bit order of value
178 This function reverses the bit order of the given value.
180 \param [in] value Value to reverse
181 \return Reversed value
183 #define __RBIT __rbit
186 /** \brief LDR Exclusive (8 bit)
188 This function performs a exclusive LDR command for 8 bit value.
190 \param [in] ptr Pointer to data
191 \return value of type uint8_t at (*ptr)
193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
196 /** \brief LDR Exclusive (16 bit)
198 This function performs a exclusive LDR command for 16 bit values.
200 \param [in] ptr Pointer to data
201 \return value of type uint16_t at (*ptr)
203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
206 /** \brief LDR Exclusive (32 bit)
208 This function performs a exclusive LDR command for 32 bit values.
210 \param [in] ptr Pointer to data
211 \return value of type uint32_t at (*ptr)
213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
216 /** \brief STR Exclusive (8 bit)
218 This function performs a exclusive STR command for 8 bit values.
220 \param [in] value Value to store
221 \param [in] ptr Pointer to location
222 \return 0 Function succeeded
223 \return 1 Function failed
225 #define __STREXB(value, ptr) __strex(value, ptr)
228 /** \brief STR Exclusive (16 bit)
230 This function performs a exclusive STR command for 16 bit values.
232 \param [in] value Value to store
233 \param [in] ptr Pointer to location
234 \return 0 Function succeeded
235 \return 1 Function failed
237 #define __STREXH(value, ptr) __strex(value, ptr)
240 /** \brief STR Exclusive (32 bit)
242 This function performs a exclusive STR command for 32 bit values.
244 \param [in] value Value to store
245 \param [in] ptr Pointer to location
246 \return 0 Function succeeded
247 \return 1 Function failed
249 #define __STREXW(value, ptr) __strex(value, ptr)
252 /** \brief Remove the exclusive lock
254 This function removes the exclusive lock which is created by LDREX.
257 #define __CLREX __clrex
260 /** \brief Signed Saturate
262 This function saturates a signed value.
264 \param [in] value Value to be saturated
265 \param [in] sat Bit position to saturate to (1..32)
266 \return Saturated value
268 #define __SSAT __ssat
271 /** \brief Unsigned Saturate
273 This function saturates an unsigned value.
275 \param [in] value Value to be saturated
276 \param [in] sat Bit position to saturate to (0..31)
277 \return Saturated value
279 #define __USAT __usat
282 /** \brief Count leading zeros
284 This function counts the number of leading zeros of a data value.
286 \param [in] value Value to count the leading zeros
287 \return number of leading zeros in value
291 #endif /* (__CORTEX_M >= 0x03) */
295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
296 /* IAR iccarm specific functions */
298 #include <cmsis_iar.h>
301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
302 /* TI CCS specific functions */
304 #include <cmsis_ccs.h>
307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
308 /* GNU gcc specific functions */
310 /* Define macros for porting to both thumb1 and thumb2.
311 * For thumb1, use low register (r0-r7), specified by constrant "l"
312 * Otherwise, use general registers, specified by constrant "r" */
313 #if defined (__thumb__) && !defined (__thumb2__)
314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
321 /** \brief No Operation
323 No Operation does nothing. This instruction can be used for code alignment purposes.
325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
327 __ASM volatile ("nop");
331 /** \brief Wait For Interrupt
333 Wait For Interrupt is a hint instruction that suspends execution
334 until one of a number of events occurs.
336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
338 __ASM volatile ("wfi");
342 /** \brief Wait For Event
344 Wait For Event is a hint instruction that permits the processor to enter
345 a low-power state until one of a number of events occurs.
347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
349 __ASM volatile ("wfe");
353 /** \brief Send Event
355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
359 __ASM volatile ("sev");
363 /** \brief Instruction Synchronization Barrier
365 Instruction Synchronization Barrier flushes the pipeline in the processor,
366 so that all instructions following the ISB are fetched from cache or
367 memory, after the instruction has been completed.
369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
371 __ASM volatile ("isb");
375 /** \brief Data Synchronization Barrier
377 This function acts as a special kind of Data Memory Barrier.
378 It completes when all explicit memory accesses before this instruction complete.
380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
382 __ASM volatile ("dsb");
386 /** \brief Data Memory Barrier
388 This function ensures the apparent order of the explicit memory operations before
389 and after the instruction, without ensuring their completion.
391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
393 __ASM volatile ("dmb");
397 /** \brief Reverse byte order (32 bit)
399 This function reverses the byte order in integer value.
401 \param [in] value Value to reverse
402 \return Reversed value
404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
407 return __builtin_bswap32(value);
411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
417 /** \brief Reverse byte order (16 bit)
419 This function reverses the byte order in two unsigned short values.
421 \param [in] value Value to reverse
422 \return Reversed value
424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
433 /** \brief Reverse byte order in signed short value
435 This function reverses the byte order in a signed short value with sign extension to integer.
437 \param [in] value Value to reverse
438 \return Reversed value
440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
443 return (short)__builtin_bswap16(value);
447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
453 /** \brief Rotate Right in unsigned value (32 bit)
455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
457 \param [in] value Value to rotate
458 \param [in] value Number of Bits to rotate
459 \return Rotated value
461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
463 return (op1 >> op2) | (op1 << (32 - op2));
467 /** \brief Breakpoint
469 This function causes the processor to enter Debug state.
470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
472 \param [in] value is ignored by the processor.
473 If required, a debugger can use it to store additional information about the breakpoint.
475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
478 #if (__CORTEX_M >= 0x03)
480 /** \brief Reverse bit order of value
482 This function reverses the bit order of the given value.
484 \param [in] value Value to reverse
485 \return Reversed value
487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
496 /** \brief LDR Exclusive (8 bit)
498 This function performs a exclusive LDR command for 8 bit value.
500 \param [in] ptr Pointer to data
501 \return value of type uint8_t at (*ptr)
503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
511 accepted by assembler. So has to use following less efficient pattern.
513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
519 /** \brief LDR Exclusive (16 bit)
521 This function performs a exclusive LDR command for 16 bit values.
523 \param [in] ptr Pointer to data
524 \return value of type uint16_t at (*ptr)
526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
534 accepted by assembler. So has to use following less efficient pattern.
536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
542 /** \brief LDR Exclusive (32 bit)
544 This function performs a exclusive LDR command for 32 bit values.
546 \param [in] ptr Pointer to data
547 \return value of type uint32_t at (*ptr)
549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
558 /** \brief STR Exclusive (8 bit)
560 This function performs a exclusive STR command for 8 bit values.
562 \param [in] value Value to store
563 \param [in] ptr Pointer to location
564 \return 0 Function succeeded
565 \return 1 Function failed
567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
576 /** \brief STR Exclusive (16 bit)
578 This function performs a exclusive STR command for 16 bit values.
580 \param [in] value Value to store
581 \param [in] ptr Pointer to location
582 \return 0 Function succeeded
583 \return 1 Function failed
585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
594 /** \brief STR Exclusive (32 bit)
596 This function performs a exclusive STR command for 32 bit values.
598 \param [in] value Value to store
599 \param [in] ptr Pointer to location
600 \return 0 Function succeeded
601 \return 1 Function failed
603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
612 /** \brief Remove the exclusive lock
614 This function removes the exclusive lock which is created by LDREX.
617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
619 __ASM volatile ("clrex" ::: "memory");
623 /** \brief Signed Saturate
625 This function saturates a signed value.
627 \param [in] value Value to be saturated
628 \param [in] sat Bit position to saturate to (1..32)
629 \return Saturated value
631 #define __SSAT(ARG1,ARG2) \
633 uint32_t __RES, __ARG1 = (ARG1); \
634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
639 /** \brief Unsigned Saturate
641 This function saturates an unsigned value.
643 \param [in] value Value to be saturated
644 \param [in] sat Bit position to saturate to (0..31)
645 \return Saturated value
647 #define __USAT(ARG1,ARG2) \
649 uint32_t __RES, __ARG1 = (ARG1); \
650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
655 /** \brief Count leading zeros
657 This function counts the number of leading zeros of a data value.
659 \param [in] value Value to count the leading zeros
660 \return number of leading zeros in value
662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
670 #endif /* (__CORTEX_M >= 0x03) */
675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
676 /* TASKING carm specific functions */
679 * The CMSIS functions have been implemented as intrinsics in the compiler.
680 * Please use "carm -?i" to get an up to date list of all intrinsics,
681 * Including the CMSIS ones.
686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
688 #endif /* __CORE_CMINSTR_H */