1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
16 #include "mbed_assert.h"
25 static const PinMap PinMap_SPI_SCLK[] = {
26 {PA_5, SPI_1, STM_PIN_DATA(2, 5)},
27 {PB_3, SPI_1, STM_PIN_DATA(2, 5)},
28 {PB_3, SPI_3, STM_PIN_DATA(2, 6)},
29 {PB_10, SPI_2, STM_PIN_DATA(2, 5)},
30 {PB_13, SPI_2, STM_PIN_DATA(2, 5)},
31 {PC_10, SPI_3, STM_PIN_DATA(2, 6)},
35 static const PinMap PinMap_SPI_MOSI[] = {
36 {PA_7, SPI_1, STM_PIN_DATA(2, 5)},
37 {PB_5, SPI_1, STM_PIN_DATA(2, 5)},
38 {PB_5, SPI_3, STM_PIN_DATA(2, 6)},
39 {PB_15, SPI_2, STM_PIN_DATA(2, 5)},
40 {PC_3, SPI_2, STM_PIN_DATA(2, 5)},
41 {PC_12, SPI_3, STM_PIN_DATA(2, 6)},
45 static const PinMap PinMap_SPI_MISO[] = {
46 {PA_6, SPI_1, STM_PIN_DATA(2, 5)},
47 {PB_4, SPI_1, STM_PIN_DATA(2, 5)},
48 {PB_4, SPI_3, STM_PIN_DATA(2, 6)},
49 {PB_14, SPI_2, STM_PIN_DATA(2, 5)},
50 {PC_2, SPI_2, STM_PIN_DATA(2, 5)},
51 {PC_11, SPI_3, STM_PIN_DATA(2, 6)},
55 static const PinMap PinMap_SPI_SSEL[] = {
56 {PA_4, SPI_1, STM_PIN_DATA(2, 5)},
57 {PA_4, SPI_3, STM_PIN_DATA(2, 6)},
58 {PA_15, SPI_1, STM_PIN_DATA(2, 5)},
59 {PA_15, SPI_3, STM_PIN_DATA(2, 6)},
60 {PB_9, SPI_2, STM_PIN_DATA(2, 5)},
61 {PB_12, SPI_2, STM_PIN_DATA(2, 5)},
66 static inline int ssp_disable(spi_t *obj);
67 static inline int ssp_enable(spi_t *obj);
69 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
70 // determine the SPI to use
71 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
72 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
73 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
74 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
75 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
76 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
77 obj->spi = (SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl);
78 MBED_ASSERT((int)obj->spi != NC);
80 // enable power and clocking
81 switch ((int)obj->spi) {
83 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN;
84 RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
87 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN;
88 RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
91 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN;
92 RCC->APB1ENR |= RCC_APB1ENR_SPI3EN;
97 // set default format and frequency
99 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
101 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
103 spi_frequency(obj, 1000000);
105 // enable the ssp channel
108 // pin out the spi pins
109 pinmap_pinout(mosi, PinMap_SPI_MOSI);
110 pinmap_pinout(miso, PinMap_SPI_MISO);
111 pinmap_pinout(sclk, PinMap_SPI_SCLK);
113 pinmap_pinout(ssel, PinMap_SPI_SSEL);
116 // Use software slave management
117 obj->spi->CR1 |= SPI_CR1_SSM | SPI_CR1_SSI;
121 void spi_free(spi_t *obj) {}
123 void spi_format(spi_t *obj, int bits, int mode, int slave) {
124 MBED_ASSERT(((bits == 8) || (bits == 16)) && ((mode >= 0) && (mode <= 3)));
127 int polarity = (mode & 0x2) ? 1 : 0;
128 int phase = (mode & 0x1) ? 1 : 0;
130 obj->spi->CR1 &= ~0x807;
131 obj->spi->CR1 |= ((phase) ? 1 : 0) << 0 |
132 ((polarity) ? 1 : 0) << 1 |
133 ((slave) ? 0: 1) << 2 |
134 ((bits == 16) ? 1 : 0) << 11;
136 if (obj->spi->SR & SPI_SR_MODF) {
137 obj->spi->CR1 = obj->spi->CR1;
143 void spi_frequency(spi_t *obj, int hz) {
146 // SPI1 runs from PCLK2, which runs at SystemCoreClock / 2. SPI2 and SPI3
147 // run from PCLK1, which runs at SystemCoreClock / 4.
148 uint32_t PCLK = SystemCoreClock;
149 switch ((int)obj->spi) {
150 case SPI_1: PCLK = PCLK >> 1; break;
151 case SPI_2: PCLK = PCLK >> 2; break;
152 case SPI_3: PCLK = PCLK >> 2; break;
155 // Choose the baud rate divisor (between 2 and 256)
156 uint32_t divisor = PCLK / hz;
158 // Find the nearest power-of-2
159 divisor = divisor > 0 ? divisor-1 : 0;
160 divisor |= divisor >> 1;
161 divisor |= divisor >> 2;
162 divisor |= divisor >> 4;
163 divisor |= divisor >> 8;
164 divisor |= divisor >> 16;
167 uint32_t baud_rate = __builtin_ffs(divisor) - 1;
168 baud_rate = baud_rate > 0x7 ? 0x7 : baud_rate;
170 obj->spi->CR1 &= ~(0x7 << 3);
171 obj->spi->CR1 |= baud_rate << 3;
176 static inline int ssp_disable(spi_t *obj) {
177 // TODO: Follow the instructions in 25.3.8 for safely disabling the SPI
178 return obj->spi->CR1 &= ~SPI_CR1_SPE;
181 static inline int ssp_enable(spi_t *obj) {
182 return obj->spi->CR1 |= SPI_CR1_SPE;
185 static inline int ssp_readable(spi_t *obj) {
186 return obj->spi->SR & SPI_SR_RXNE;
189 static inline int ssp_writeable(spi_t *obj) {
190 return obj->spi->SR & SPI_SR_TXE;
193 static inline void ssp_write(spi_t *obj, int value) {
194 while (!ssp_writeable(obj));
195 obj->spi->DR = value;
198 static inline int ssp_read(spi_t *obj) {
199 while (!ssp_readable(obj));
203 static inline int ssp_busy(spi_t *obj) {
204 return (obj->spi->SR & SPI_SR_BSY) ? (1) : (0);
207 int spi_master_write(spi_t *obj, int value) {
208 ssp_write(obj, value);
209 return ssp_read(obj);
212 int spi_slave_receive(spi_t *obj) {
213 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
216 int spi_slave_read(spi_t *obj) {
220 void spi_slave_write(spi_t *obj, int value) {
221 while (ssp_writeable(obj) == 0) ;
222 obj->spi->DR = value;
225 int spi_busy(spi_t *obj) {
226 return ssp_busy(obj);