1 /* mbed USBHost Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 #if defined(TARGET_LPC1768)
20 #include "USBHALHost.h"
23 // bits of the USB/OTG clock control register
24 #define HOST_CLK_EN (1<<0)
25 #define DEV_CLK_EN (1<<1)
26 #define PORTSEL_CLK_EN (1<<3)
27 #define AHB_CLK_EN (1<<4)
29 // bits of the USB/OTG clock status register
30 #define HOST_CLK_ON (1<<0)
31 #define DEV_CLK_ON (1<<1)
32 #define PORTSEL_CLK_ON (1<<3)
33 #define AHB_CLK_ON (1<<4)
35 // we need host clock, OTG/portsel clock and AHB clock
36 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
38 #define HCCA_SIZE sizeof(HCCA)
39 #define ED_SIZE sizeof(HCED)
40 #define TD_SIZE sizeof(HCTD)
42 #define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
44 static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256))); //256 bytes aligned!
46 USBHALHost * USBHALHost::instHost;
48 USBHALHost::USBHALHost() {
51 memset((void*)usb_hcca, 0, HCCA_SIZE);
52 for (int i = 0; i < MAX_ENDPOINT; i++) {
53 edBufAlloc[i] = false;
55 for (int i = 0; i < MAX_TD; i++) {
56 tdBufAlloc[i] = false;
60 void USBHALHost::init() {
61 NVIC_DisableIRQ(USB_IRQn);
64 LPC_SC->PCONP &= ~(1UL<<31);
67 // turn on power for USB
68 LPC_SC->PCONP |= (1UL<<31);
70 // Enable USB host clock, port selection and AHB clock
71 LPC_USB->USBClkCtrl |= CLOCK_MASK;
73 // Wait for clocks to become available
74 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
76 // it seems the bits[0:1] mean the following
77 // 0: U1=device, U2=host
78 // 1: U1=host, U2=host
80 // 3: U1=host, U2=device
81 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
82 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
83 LPC_USB->OTGStCtrl |= 1;
85 // now that we've configured the ports, we can turn off the portsel clock
86 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
88 // configure USB D+/D- pins
89 // P0[29] = USB_D+, 01
90 // P0[30] = USB_D-, 01
91 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
92 LPC_PINCON->PINSEL1 |= ((1<<26) | (1<<28));
94 LPC_USB->HcControl = 0; // HARDWARE RESET
95 LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
96 LPC_USB->HcBulkHeadED = 0; // Initialize Bulk list head to Zero
98 // Wait 100 ms before apply reset
102 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
104 // Write Fm Interval and Largest Data Packet Counter
105 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL;
106 LPC_USB->HcPeriodicStart = FI * 90 / 100;
108 // Put HC in operational state
109 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
111 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
113 LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
115 // Clear Interrrupt Status
116 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
118 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
120 // Enable the USB Interrupt
121 NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
122 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
123 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
125 NVIC_EnableIRQ(USB_IRQn);
127 // Check for any connected devices
128 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
131 USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
132 deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
136 uint32_t USBHALHost::controlHeadED() {
137 return LPC_USB->HcControlHeadED;
140 uint32_t USBHALHost::bulkHeadED() {
141 return LPC_USB->HcBulkHeadED;
144 uint32_t USBHALHost::interruptHeadED() {
145 return usb_hcca->IntTable[0];
148 void USBHALHost::updateBulkHeadED(uint32_t addr) {
149 LPC_USB->HcBulkHeadED = addr;
153 void USBHALHost::updateControlHeadED(uint32_t addr) {
154 LPC_USB->HcControlHeadED = addr;
157 void USBHALHost::updateInterruptHeadED(uint32_t addr) {
158 usb_hcca->IntTable[0] = addr;
162 void USBHALHost::enableList(ENDPOINT_TYPE type) {
164 case CONTROL_ENDPOINT:
165 LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
166 LPC_USB->HcControl |= OR_CONTROL_CLE;
168 case ISOCHRONOUS_ENDPOINT:
171 LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
172 LPC_USB->HcControl |= OR_CONTROL_BLE;
174 case INTERRUPT_ENDPOINT:
175 LPC_USB->HcControl |= OR_CONTROL_PLE;
181 bool USBHALHost::disableList(ENDPOINT_TYPE type) {
183 case CONTROL_ENDPOINT:
184 if(LPC_USB->HcControl & OR_CONTROL_CLE) {
185 LPC_USB->HcControl &= ~OR_CONTROL_CLE;
189 case ISOCHRONOUS_ENDPOINT:
192 if(LPC_USB->HcControl & OR_CONTROL_BLE){
193 LPC_USB->HcControl &= ~OR_CONTROL_BLE;
197 case INTERRUPT_ENDPOINT:
198 if(LPC_USB->HcControl & OR_CONTROL_PLE) {
199 LPC_USB->HcControl &= ~OR_CONTROL_PLE;
208 void USBHALHost::memInit() {
209 usb_hcca = (volatile HCCA *)usb_buf;
210 usb_edBuf = usb_buf + HCCA_SIZE;
211 usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
214 volatile uint8_t * USBHALHost::getED() {
215 for (int i = 0; i < MAX_ENDPOINT; i++) {
216 if ( !edBufAlloc[i] ) {
217 edBufAlloc[i] = true;
218 return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
221 perror("Could not allocate ED\r\n");
222 return NULL; //Could not alloc ED
225 volatile uint8_t * USBHALHost::getTD() {
227 for (i = 0; i < MAX_TD; i++) {
228 if ( !tdBufAlloc[i] ) {
229 tdBufAlloc[i] = true;
230 return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
233 perror("Could not allocate TD\r\n");
234 return NULL; //Could not alloc TD
238 void USBHALHost::freeED(volatile uint8_t * ed) {
240 i = (ed - usb_edBuf) / ED_SIZE;
241 edBufAlloc[i] = false;
244 void USBHALHost::freeTD(volatile uint8_t * td) {
246 i = (td - usb_tdBuf) / TD_SIZE;
247 tdBufAlloc[i] = false;
251 void USBHALHost::resetRootHub() {
252 // Initiate port reset
253 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
255 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
257 // ...and clear port reset signal
258 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
262 void USBHALHost::_usbisr(void) {
264 instHost->UsbIrqhandler();
268 void USBHALHost::UsbIrqhandler() {
269 if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
272 uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
274 // Root hub status change interrupt
275 if (int_status & OR_INTR_STATUS_RHSC) {
276 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
277 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
278 // When DRWE is on, Connect Status Change
279 // means a remote wakeup event.
282 //Root device connected
283 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
285 // wait 150ms to avoid bounce
288 //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
289 deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
292 //Root device disconnected
295 if (!(int_status & OR_INTR_STATUS_WDH)) {
296 usb_hcca->DoneHead = 0;
299 // wait 200ms to avoid bounce
302 deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
304 if (int_status & OR_INTR_STATUS_WDH) {
305 usb_hcca->DoneHead = 0;
306 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
310 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
312 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
313 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
315 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
318 // Writeback Done Head interrupt
319 if (int_status & OR_INTR_STATUS_WDH) {
320 transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
321 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;