2 ******************************************************************************
3 * @file stm32l1xx_hal.h
4 * @author MCD Application Team
6 * @date 5-September-2014
7 * @brief This file contains all the functions prototypes for the HAL
9 ******************************************************************************
12 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
14 * Redistribution and use in source and binary forms, with or without modification,
15 * are permitted provided that the following conditions are met:
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 ******************************************************************************
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef __STM32L1xx_HAL_H
41 #define __STM32L1xx_HAL_H
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32l1xx_hal_conf.h"
50 /** @addtogroup STM32L1xx_HAL_Driver
58 /* Exported types ------------------------------------------------------------*/
59 /* Exported constants --------------------------------------------------------*/
60 /** @defgroup HAL_Exported_Constants HAL Exported Constants
64 /** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG
68 /** @defgroup SYSCFG_BootMode Boot Mode
72 #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
73 #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
74 #if defined(FSMC_R_BASE)
75 #define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
76 #endif /* FSMC_R_BASE */
77 #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)
87 /** @defgroup RI_Constants RI: Routing Interface
91 /** @defgroup RI_InputCapture Input Capture
95 #define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */
96 #define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */
97 #define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */
98 #define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */
104 /** @defgroup TIM_Select TIM Select
108 #define TIM_SELECT_NONE ((uint32_t)0x00000000) /*!< None selected */
109 #define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */
110 #define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */
111 #define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */
113 #define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \
114 ((__TIM__) == TIM_SELECT_TIM2) || \
115 ((__TIM__) == TIM_SELECT_TIM3) || \
116 ((__TIM__) == TIM_SELECT_TIM4))
122 /** @defgroup RI_InputCaptureRouting Input Capture Routing
125 /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
126 #define RI_INPUTCAPTUREROUTING_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */
127 #define RI_INPUTCAPTUREROUTING_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */
128 #define RI_INPUTCAPTUREROUTING_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */
129 #define RI_INPUTCAPTUREROUTING_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */
130 #define RI_INPUTCAPTUREROUTING_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */
131 #define RI_INPUTCAPTUREROUTING_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */
132 #define RI_INPUTCAPTUREROUTING_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */
133 #define RI_INPUTCAPTUREROUTING_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */
134 #define RI_INPUTCAPTUREROUTING_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */
135 #define RI_INPUTCAPTUREROUTING_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */
136 #define RI_INPUTCAPTUREROUTING_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */
137 #define RI_INPUTCAPTUREROUTING_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */
138 #define RI_INPUTCAPTUREROUTING_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */
139 #define RI_INPUTCAPTUREROUTING_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */
140 #define RI_INPUTCAPTUREROUTING_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */
141 #define RI_INPUTCAPTUREROUTING_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */
143 #define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \
144 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \
145 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \
146 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \
147 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \
148 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \
149 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \
150 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \
151 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \
152 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \
153 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \
154 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \
155 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \
156 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \
157 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \
158 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))
164 /** @defgroup RI_IOSwitch IO Switch
167 #define RI_ASCR1_REGISTER ((uint32_t)0x80000000)
168 /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
169 #define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)
170 #define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)
171 #define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)
172 #define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)
173 #define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)
174 #define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)
175 #define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)
176 #define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)
177 #define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)
178 #define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)
179 #define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)
180 #define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)
181 #define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)
182 #define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)
183 #define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)
184 #define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)
185 #define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)
186 #define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)
187 #define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)
188 #define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)
189 #define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)
190 #define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)
191 #define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)
192 #define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)
193 #define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */
194 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
195 #define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)
196 #define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)
197 #define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)
198 #define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)
199 #define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)
200 #endif /* RI_ASCR2_CH1b */
202 /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
203 #define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1)
204 #define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2)
205 #define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3)
206 #define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4)
207 #define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1)
208 #define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2)
209 #define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1)
210 #define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2)
211 #define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3)
212 #define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1)
213 #define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2)
214 #define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3)
215 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */
216 #define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b)
217 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
218 #define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b)
219 #define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b)
220 #define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b)
221 #define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b)
222 #define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b)
223 #define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b)
224 #define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b)
225 #define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b)
226 #define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b)
227 #define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b)
228 #endif /* RI_ASCR2_CH1b */
229 #define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3)
230 #define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4)
231 #endif /* RI_ASCR2_CH0b */
234 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
236 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
237 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
238 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
239 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
240 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
241 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
242 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
243 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
244 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
245 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
246 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
247 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
248 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \
249 ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \
250 ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \
251 ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \
252 ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \
253 ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \
254 ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \
255 ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \
256 ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \
257 ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \
258 ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \
259 ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \
260 ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \
261 ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \
262 ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \
263 ((__IOSWITCH__) == RI_IOSWITCH_CH12b))
265 #else /* !RI_ASCR2_CH1b */
267 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */
269 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
270 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
271 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
272 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
273 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
274 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
275 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
276 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
277 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
278 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
279 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
280 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
281 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
282 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
283 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \
284 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \
285 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \
286 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \
287 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))
289 #else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */
291 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
292 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
293 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
294 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
295 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
296 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
297 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
298 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
299 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
300 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
301 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
302 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
303 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
304 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
305 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \
306 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \
307 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \
308 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \
309 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3))
311 #endif /* RI_ASCR2_CH0b */
312 #endif /* RI_ASCR2_CH1b */
318 /** @defgroup RI_Pin PIN define
321 #define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
322 #define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
323 #define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
324 #define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
325 #define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
326 #define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
327 #define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
328 #define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
329 #define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
330 #define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
331 #define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
332 #define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
333 #define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
334 #define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
335 #define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
336 #define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
337 #define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
339 #define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)
353 /* Exported macro ------------------------------------------------------------*/
355 /** @defgroup HAL_Exported_Macros HAL Exported Macros
359 /** @defgroup DBGMCU_Macros DBGMCU: Debug MCU
363 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
364 * @brief Freeze/Unfreeze Peripherals in Debug mode
369 * @brief TIM2 Peripherals Debug mode
371 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
372 #define __HAL_FREEZE_TIM2_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
373 #define __HAL_UNFREEZE_TIM2_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
377 * @brief TIM3 Peripherals Debug mode
379 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
380 #define __HAL_FREEZE_TIM3_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
381 #define __HAL_UNFREEZE_TIM3_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
385 * @brief TIM4 Peripherals Debug mode
387 #if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)
388 #define __HAL_FREEZE_TIM4_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
389 #define __HAL_UNFREEZE_TIM4_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
393 * @brief TIM5 Peripherals Debug mode
395 #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
396 #define __HAL_FREEZE_TIM5_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
397 #define __HAL_UNFREEZE_TIM5_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
401 * @brief TIM6 Peripherals Debug mode
403 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
404 #define __HAL_FREEZE_TIM6_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
405 #define __HAL_UNFREEZE_TIM6_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
409 * @brief TIM7 Peripherals Debug mode
411 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
412 #define __HAL_FREEZE_TIM7_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
413 #define __HAL_UNFREEZE_TIM7_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
417 * @brief RTC Peripherals Debug mode
419 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
420 #define __HAL_FREEZE_RTC_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
421 #define __HAL_UNFREEZE_RTC_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
425 * @brief WWDG Peripherals Debug mode
427 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
428 #define __HAL_FREEZE_WWDG_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
429 #define __HAL_UNFREEZE_WWDG_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
433 * @brief IWDG Peripherals Debug mode
435 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
436 #define __HAL_FREEZE_IWDG_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
437 #define __HAL_UNFREEZE_IWDG_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
441 * @brief I2C1 Peripherals Debug mode
443 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
444 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
445 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
449 * @brief I2C2 Peripherals Debug mode
451 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
452 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
453 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
457 * @brief TIM9 Peripherals Debug mode
459 #if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)
460 #define __HAL_FREEZE_TIM9_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
461 #define __HAL_UNFREEZE_TIM9_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
465 * @brief TIM10 Peripherals Debug mode
467 #if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)
468 #define __HAL_FREEZE_TIM10_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
469 #define __HAL_UNFREEZE_TIM10_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
473 * @brief TIM11 Peripherals Debug mode
475 #if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)
476 #define __HAL_FREEZE_TIM11_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
477 #define __HAL_UNFREEZE_TIM11_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
481 * @brief Enables or disables the output of internal reference voltage
482 * (VREFINT) on I/O pin.
483 * The VREFINT output can be routed to any I/O in group 3:
484 * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
485 * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
486 * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),
487 * CH1b (PF11) or CH2b (PF12).
488 * Note: Comparator peripheral clock must be preliminarility enabled,
489 * either in COMP user function "HAL_COMP_MspInit()" (should be
490 * done if comparators are used) or by direct clock enable:
491 * Refer to macro "__COMP_CLK_ENABLE()".
492 * Note: In addition with this macro, Vrefint output buffer must be
493 * connected to the selected I/O pin. Refer to macro
494 * "__HAL_RI_IOSWITCH_CLOSE()".
495 * @note ENABLE: Internal reference voltage connected to I/O group 3
496 * @note DISABLE: Internal reference voltage disconnected from I/O group 3
499 #define __HAL_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
500 #define __HAL_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
510 /** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG
514 /** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration
519 * @brief Main Flash memory mapped at 0x00000000
521 #define __HAL_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
523 /** @brief System Flash memory mapped at 0x00000000
525 #define __HAL_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
527 /** @brief Embedded SRAM mapped at 0x00000000
529 #define __HAL_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)
531 #if defined(FSMC_R_BASE)
532 /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
534 #define __HAL_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
536 #endif /* FSMC_R_BASE */
539 * @brief Returns the boot mode as configured by user.
540 * @retval The boot mode as configured by user. The returned value can be one
541 * of the following values:
542 * @arg SYSCFG_BOOT_MAINFLASH
543 * @arg SYSCFG_BOOT_SYSTEMFLASH
544 * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)
545 * @arg SYSCFG_BOOT_SRAM
547 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)
553 /** @defgroup SYSCFG_USBConfig USB DP line Configuration
558 * @brief Control the internal pull-up on USB DP line.
560 #define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
562 #define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
572 /** @defgroup RI_Macris RI: Routing Interface
576 /** @defgroup RI_InputCaputureConfig Input Capture configuration
581 * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.
582 * @param __TIMSELECT__: Timer select.
583 * This parameter can be one of the following values:
584 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
585 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
586 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
587 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
588 * @param __INPUT__: selects which pin to be routed to Input Capture.
589 * This parameter must be a value of @ref RI_InputCaptureRouting
591 * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)
592 * allows routing of Input capture IC1 of TIM2 to PA4.
593 * For details about correspondence between RI_INPUTCAPTUREROUTING_x
594 * and I/O pins refer to the parameters' description in the header file
595 * or refer to the product reference manual.
596 * @note Input capture selection bits are not reset by this function.
597 * To reset input capture selection bits, use SYSCFG_RIDeInit() function.
598 * @note The I/O should be configured in alternate function mode (AF14) using
599 * GPIO_PinAFConfig() function.
602 #define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \
603 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
604 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
605 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
606 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
607 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
611 * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.
612 * @param __TIMSELECT__: Timer select.
613 * This parameter can be one of the following values:
614 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
615 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
616 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
617 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
618 * @param __INPUT__: selects which pin to be routed to Input Capture.
619 * This parameter must be a value of @ref RI_InputCaptureRouting
622 #define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \
623 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
624 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
625 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
626 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
627 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
631 * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.
632 * @param __TIMSELECT__: Timer select.
633 * This parameter can be one of the following values:
634 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
635 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
636 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
637 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
638 * @param __INPUT__: selects which pin to be routed to Input Capture.
639 * This parameter must be a value of @ref RI_InputCaptureRouting
642 #define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \
643 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
644 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
645 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
646 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
647 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
651 * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.
652 * @param __TIMSELECT__: Timer select.
653 * This parameter can be one of the following values:
654 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
655 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
656 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
657 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
658 * @param __INPUT__: selects which pin to be routed to Input Capture.
659 * This parameter must be a value of @ref RI_InputCaptureRouting
662 #define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \
663 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
664 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
665 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
666 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \
667 MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \
674 /** @defgroup RI_SwitchControlConfig Switch Control configuration
679 * @brief Enable or disable the switch control mode.
680 * @note ENABLE: ADC analog switches closed if the corresponding
681 * I/O switch is also closed.
682 * When using COMP1, switch control mode must be enabled.
683 * @note DISABLE: ADC analog switches open or controlled by the ADC interface.
684 * When using the ADC for acquisition, switch control mode
686 * @note COMP1 comparator and ADC cannot be used at the same time since
687 * they share the ADC switch matrix.
690 #define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM)
692 #define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)
695 * @brief Close or Open the routing interface Input Output switches.
696 * @param __IOSWITCH__: selects the I/O analog switch number.
697 * This parameter must be a value of @ref RI_IOSwitch
700 #define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
701 if ((__IOSWITCH__) >> 31 != 0 ) \
703 SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
707 SET_BIT(RI->ASCR2, (__IOSWITCH__)); \
711 #define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
712 if ((__IOSWITCH__) >> 31 != 0 ) \
714 CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
718 CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \
722 #if defined (COMP_CSR_SW1)
724 * @brief Close or open the internal switch COMP1_SW1.
725 * This switch connects I/O pin PC3 (can be used as ADC channel 13)
726 * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel
727 * 26) and COMP1 non-inverting input.
728 * Pin PC3 connection depends on another switch setting, refer to
729 * macro "__HAL_ADC_CHANNEL_SPEED_FAST()".
732 #define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1)
734 #define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)
735 #endif /* COMP_CSR_SW1 */
741 /** @defgroup RI_HystConfig Hysteresis Activation and Deactivation
746 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A
747 * When the I/Os are programmed in input mode by standard I/O port
748 * registers, the Schmitt trigger and the hysteresis are enabled by default.
749 * When hysteresis is disabled, it is possible to read the
750 * corresponding port with a trigger level of VDDIO/2.
751 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
752 * This parameter must be a value of @ref RI_Pin
755 #define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
756 CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \
759 #define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
760 SET_BIT(RI->HYSCR1, (__IOPIN__)); \
764 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B
765 * When the I/Os are programmed in input mode by standard I/O port
766 * registers, the Schmitt trigger and the hysteresis are enabled by default.
767 * When hysteresis is disabled, it is possible to read the
768 * corresponding port with a trigger level of VDDIO/2.
769 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
770 * This parameter must be a value of @ref RI_Pin
773 #define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
774 CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
777 #define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
778 SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
782 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C
783 * When the I/Os are programmed in input mode by standard I/O port
784 * registers, the Schmitt trigger and the hysteresis are enabled by default.
785 * When hysteresis is disabled, it is possible to read the
786 * corresponding port with a trigger level of VDDIO/2.
787 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
788 * This parameter must be a value of @ref RI_Pin
791 #define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
792 CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \
795 #define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
796 SET_BIT(RI->HYSCR2, (__IOPIN__)); \
800 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D
801 * When the I/Os are programmed in input mode by standard I/O port
802 * registers, the Schmitt trigger and the hysteresis are enabled by default.
803 * When hysteresis is disabled, it is possible to read the
804 * corresponding port with a trigger level of VDDIO/2.
805 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
806 * This parameter must be a value of @ref RI_Pin
809 #define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
810 CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
813 #define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
814 SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
817 #if defined (GPIOE_BASE)
820 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E
821 * When the I/Os are programmed in input mode by standard I/O port
822 * registers, the Schmitt trigger and the hysteresis are enabled by default.
823 * When hysteresis is disabled, it is possible to read the
824 * corresponding port with a trigger level of VDDIO/2.
825 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
826 * This parameter must be a value of @ref RI_Pin
829 #define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
830 CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \
833 #define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
834 SET_BIT(RI->HYSCR3, (__IOPIN__)); \
837 #endif /* GPIOE_BASE */
839 #if defined(GPIOF_BASE) || defined(GPIOG_BASE)
842 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F
843 * When the I/Os are programmed in input mode by standard I/O port
844 * registers, the Schmitt trigger and the hysteresis are enabled by default.
845 * When hysteresis is disabled, it is possible to read the
846 * corresponding port with a trigger level of VDDIO/2.
847 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
848 * This parameter must be a value of @ref RI_Pin
851 #define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
852 CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
855 #define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
856 SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
860 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G
861 * When the I/Os are programmed in input mode by standard I/O port
862 * registers, the Schmitt trigger and the hysteresis are enabled by default.
863 * When hysteresis is disabled, it is possible to read the
864 * corresponding port with a trigger level of VDDIO/2.
865 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
866 * This parameter must be a value of @ref RI_Pin
869 #define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
870 CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \
873 #define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
874 SET_BIT(RI->HYSCR4, (__IOPIN__)); \
877 #endif /* GPIOF_BASE || GPIOG_BASE */
891 /* Exported functions --------------------------------------------------------*/
893 /** @addtogroup HAL_Exported_Functions
897 /** @addtogroup HAL_Exported_Functions_Group1
901 /* Initialization and de-initialization functions ******************************/
902 HAL_StatusTypeDef HAL_Init(void);
903 HAL_StatusTypeDef HAL_DeInit(void);
904 void HAL_MspInit(void);
905 void HAL_MspDeInit(void);
906 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
912 /** @addtogroup HAL_Exported_Functions_Group2
916 /* Peripheral Control functions ************************************************/
917 void HAL_IncTick(void);
918 void HAL_Delay(__IO uint32_t Delay);
919 uint32_t HAL_GetTick(void);
920 void HAL_SuspendTick(void);
921 void HAL_ResumeTick(void);
922 uint32_t HAL_GetHalVersion(void);
923 uint32_t HAL_GetREVID(void);
924 uint32_t HAL_GetDEVID(void);
925 void HAL_EnableDBGSleepMode(void);
926 void HAL_DisableDBGSleepMode(void);
927 void HAL_EnableDBGStopMode(void);
928 void HAL_DisableDBGStopMode(void);
929 void HAL_EnableDBGStandbyMode(void);
930 void HAL_DisableDBGStandbyMode(void);
953 #endif /* __STM32L1xx_HAL_H */
955 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/