2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_FTM_REGISTERS_H__
81 #define __HW_FTM_REGISTERS_H__
84 #include "fsl_bitaccess.h"
91 * Registers defined in this header file:
92 * - HW_FTM_SC - Status And Control
93 * - HW_FTM_CNT - Counter
94 * - HW_FTM_MOD - Modulo
95 * - HW_FTM_CnSC - Channel (n) Status And Control
96 * - HW_FTM_CnV - Channel (n) Value
97 * - HW_FTM_CNTIN - Counter Initial Value
98 * - HW_FTM_STATUS - Capture And Compare Status
99 * - HW_FTM_MODE - Features Mode Selection
100 * - HW_FTM_SYNC - Synchronization
101 * - HW_FTM_OUTINIT - Initial State For Channels Output
102 * - HW_FTM_OUTMASK - Output Mask
103 * - HW_FTM_COMBINE - Function For Linked Channels
104 * - HW_FTM_DEADTIME - Deadtime Insertion Control
105 * - HW_FTM_EXTTRIG - FTM External Trigger
106 * - HW_FTM_POL - Channels Polarity
107 * - HW_FTM_FMS - Fault Mode Status
108 * - HW_FTM_FILTER - Input Capture Filter Control
109 * - HW_FTM_FLTCTRL - Fault Control
110 * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
111 * - HW_FTM_CONF - Configuration
112 * - HW_FTM_FLTPOL - FTM Fault Input Polarity
113 * - HW_FTM_SYNCONF - Synchronization Configuration
114 * - HW_FTM_INVCTRL - FTM Inverting Control
115 * - HW_FTM_SWOCTRL - FTM Software Output Control
116 * - HW_FTM_PWMLOAD - FTM PWM Load
118 * - hw_ftm_t - Struct containing all module registers.
121 #define HW_FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
122 #define HW_FTM0 (0U) /*!< Instance number for FTM0. */
123 #define HW_FTM1 (1U) /*!< Instance number for FTM1. */
124 #define HW_FTM2 (2U) /*!< Instance number for FTM2. */
125 #define HW_FTM3 (3U) /*!< Instance number for FTM3. */
127 /*******************************************************************************
128 * HW_FTM_SC - Status And Control
129 ******************************************************************************/
132 * @brief HW_FTM_SC - Status And Control (RW)
134 * Reset value: 0x00000000U
136 * SC contains the overflow status flag and control bits used to configure the
137 * interrupt enable, FTM configuration, clock source, and prescaler factor. These
138 * controls relate to all channels within this module.
140 typedef union _hw_ftm_sc
143 struct _hw_ftm_sc_bitfields
145 uint32_t PS : 3; /*!< [2:0] Prescale Factor Selection */
146 uint32_t CLKS : 2; /*!< [4:3] Clock Source Selection */
147 uint32_t CPWMS : 1; /*!< [5] Center-Aligned PWM Select */
148 uint32_t TOIE : 1; /*!< [6] Timer Overflow Interrupt Enable */
149 uint32_t TOF : 1; /*!< [7] Timer Overflow Flag */
150 uint32_t RESERVED0 : 24; /*!< [31:8] */
155 * @name Constants and macros for entire FTM_SC register
158 #define HW_FTM_SC_ADDR(x) ((x) + 0x0U)
160 #define HW_FTM_SC(x) (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x))
161 #define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U)
162 #define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v))
163 #define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) | (v)))
164 #define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
165 #define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v)))
169 * Constants & macros for individual FTM_SC bitfields
173 * @name Register FTM_SC, field PS[2:0] (RW)
175 * Selects one of 8 division factors for the clock source selected by CLKS. The
176 * new prescaler factor affects the clock source on the next system clock cycle
177 * after the new value is updated into the register bits. This field is write
178 * protected. It can be written only when MODE[WPDIS] = 1.
181 * - 000 - Divide by 1
182 * - 001 - Divide by 2
183 * - 010 - Divide by 4
184 * - 011 - Divide by 8
185 * - 100 - Divide by 16
186 * - 101 - Divide by 32
187 * - 110 - Divide by 64
188 * - 111 - Divide by 128
191 #define BP_FTM_SC_PS (0U) /*!< Bit position for FTM_SC_PS. */
192 #define BM_FTM_SC_PS (0x00000007U) /*!< Bit mask for FTM_SC_PS. */
193 #define BS_FTM_SC_PS (3U) /*!< Bit field size in bits for FTM_SC_PS. */
195 /*! @brief Read current value of the FTM_SC_PS field. */
196 #define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS)
198 /*! @brief Format value for bitfield FTM_SC_PS. */
199 #define BF_FTM_SC_PS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_PS) & BM_FTM_SC_PS)
201 /*! @brief Set the PS field to a new value. */
202 #define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v)))
206 * @name Register FTM_SC, field CLKS[4:3] (RW)
208 * Selects one of the three FTM counter clock sources. This field is write
209 * protected. It can be written only when MODE[WPDIS] = 1.
212 * - 00 - No clock selected. This in effect disables the FTM counter.
213 * - 01 - System clock
214 * - 10 - Fixed frequency clock
215 * - 11 - External clock
218 #define BP_FTM_SC_CLKS (3U) /*!< Bit position for FTM_SC_CLKS. */
219 #define BM_FTM_SC_CLKS (0x00000018U) /*!< Bit mask for FTM_SC_CLKS. */
220 #define BS_FTM_SC_CLKS (2U) /*!< Bit field size in bits for FTM_SC_CLKS. */
222 /*! @brief Read current value of the FTM_SC_CLKS field. */
223 #define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS)
225 /*! @brief Format value for bitfield FTM_SC_CLKS. */
226 #define BF_FTM_SC_CLKS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CLKS) & BM_FTM_SC_CLKS)
228 /*! @brief Set the CLKS field to a new value. */
229 #define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v)))
233 * @name Register FTM_SC, field CPWMS[5] (RW)
235 * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
236 * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
240 * - 0 - FTM counter operates in Up Counting mode.
241 * - 1 - FTM counter operates in Up-Down Counting mode.
244 #define BP_FTM_SC_CPWMS (5U) /*!< Bit position for FTM_SC_CPWMS. */
245 #define BM_FTM_SC_CPWMS (0x00000020U) /*!< Bit mask for FTM_SC_CPWMS. */
246 #define BS_FTM_SC_CPWMS (1U) /*!< Bit field size in bits for FTM_SC_CPWMS. */
248 /*! @brief Read current value of the FTM_SC_CPWMS field. */
249 #define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
251 /*! @brief Format value for bitfield FTM_SC_CPWMS. */
252 #define BF_FTM_SC_CPWMS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CPWMS) & BM_FTM_SC_CPWMS)
254 /*! @brief Set the CPWMS field to a new value. */
255 #define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
259 * @name Register FTM_SC, field TOIE[6] (RW)
261 * Enables FTM overflow interrupts.
264 * - 0 - Disable TOF interrupts. Use software polling.
265 * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
268 #define BP_FTM_SC_TOIE (6U) /*!< Bit position for FTM_SC_TOIE. */
269 #define BM_FTM_SC_TOIE (0x00000040U) /*!< Bit mask for FTM_SC_TOIE. */
270 #define BS_FTM_SC_TOIE (1U) /*!< Bit field size in bits for FTM_SC_TOIE. */
272 /*! @brief Read current value of the FTM_SC_TOIE field. */
273 #define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
275 /*! @brief Format value for bitfield FTM_SC_TOIE. */
276 #define BF_FTM_SC_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOIE) & BM_FTM_SC_TOIE)
278 /*! @brief Set the TOIE field to a new value. */
279 #define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
283 * @name Register FTM_SC, field TOF[7] (ROWZ)
285 * Set by hardware when the FTM counter passes the value in the MOD register.
286 * The TOF bit is cleared by reading the SC register while TOF is set and then
287 * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
288 * occurs between the read and write operations, the write operation has no
289 * effect; therefore, TOF remains set indicating an overflow has occurred. In this
290 * case, a TOF interrupt request is not lost due to the clearing sequence for a
294 * - 0 - FTM counter has not overflowed.
295 * - 1 - FTM counter has overflowed.
298 #define BP_FTM_SC_TOF (7U) /*!< Bit position for FTM_SC_TOF. */
299 #define BM_FTM_SC_TOF (0x00000080U) /*!< Bit mask for FTM_SC_TOF. */
300 #define BS_FTM_SC_TOF (1U) /*!< Bit field size in bits for FTM_SC_TOF. */
302 /*! @brief Read current value of the FTM_SC_TOF field. */
303 #define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
305 /*! @brief Format value for bitfield FTM_SC_TOF. */
306 #define BF_FTM_SC_TOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOF) & BM_FTM_SC_TOF)
308 /*! @brief Set the TOF field to a new value. */
309 #define BW_FTM_SC_TOF(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF) = (v))
312 /*******************************************************************************
313 * HW_FTM_CNT - Counter
314 ******************************************************************************/
317 * @brief HW_FTM_CNT - Counter (RW)
319 * Reset value: 0x00000000U
321 * The CNT register contains the FTM counter value. Reset clears the CNT
322 * register. Writing any value to COUNT updates the counter with its initial value,
323 * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
326 typedef union _hw_ftm_cnt
329 struct _hw_ftm_cnt_bitfields
331 uint32_t COUNT : 16; /*!< [15:0] Counter Value */
332 uint32_t RESERVED0 : 16; /*!< [31:16] */
337 * @name Constants and macros for entire FTM_CNT register
340 #define HW_FTM_CNT_ADDR(x) ((x) + 0x4U)
342 #define HW_FTM_CNT(x) (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x))
343 #define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U)
344 #define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v))
345 #define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) | (v)))
346 #define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
347 #define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v)))
351 * Constants & macros for individual FTM_CNT bitfields
355 * @name Register FTM_CNT, field COUNT[15:0] (RW)
358 #define BP_FTM_CNT_COUNT (0U) /*!< Bit position for FTM_CNT_COUNT. */
359 #define BM_FTM_CNT_COUNT (0x0000FFFFU) /*!< Bit mask for FTM_CNT_COUNT. */
360 #define BS_FTM_CNT_COUNT (16U) /*!< Bit field size in bits for FTM_CNT_COUNT. */
362 /*! @brief Read current value of the FTM_CNT_COUNT field. */
363 #define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT)
365 /*! @brief Format value for bitfield FTM_CNT_COUNT. */
366 #define BF_FTM_CNT_COUNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNT_COUNT) & BM_FTM_CNT_COUNT)
368 /*! @brief Set the COUNT field to a new value. */
369 #define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v)))
372 /*******************************************************************************
373 * HW_FTM_MOD - Modulo
374 ******************************************************************************/
377 * @brief HW_FTM_MOD - Modulo (RW)
379 * Reset value: 0x00000000U
381 * The Modulo register contains the modulo value for the FTM counter. After the
382 * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
383 * the next clock, and the next value of FTM counter depends on the selected
384 * counting method; see Counter. Writing to the MOD register latches the value into a
385 * buffer. The MOD register is updated with the value of its write buffer
386 * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
387 * mechanism may be manually reset by writing to the SC register whether BDM is
388 * active or not. Initialize the FTM counter, by writing to CNT, before writing
389 * to the MOD register to avoid confusion about when the first counter overflow
392 typedef union _hw_ftm_mod
395 struct _hw_ftm_mod_bitfields
397 uint32_t MOD : 16; /*!< [15:0] */
398 uint32_t RESERVED0 : 16; /*!< [31:16] */
403 * @name Constants and macros for entire FTM_MOD register
406 #define HW_FTM_MOD_ADDR(x) ((x) + 0x8U)
408 #define HW_FTM_MOD(x) (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x))
409 #define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U)
410 #define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v))
411 #define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) | (v)))
412 #define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
413 #define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v)))
417 * Constants & macros for individual FTM_MOD bitfields
421 * @name Register FTM_MOD, field MOD[15:0] (RW)
426 #define BP_FTM_MOD_MOD (0U) /*!< Bit position for FTM_MOD_MOD. */
427 #define BM_FTM_MOD_MOD (0x0000FFFFU) /*!< Bit mask for FTM_MOD_MOD. */
428 #define BS_FTM_MOD_MOD (16U) /*!< Bit field size in bits for FTM_MOD_MOD. */
430 /*! @brief Read current value of the FTM_MOD_MOD field. */
431 #define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD)
433 /*! @brief Format value for bitfield FTM_MOD_MOD. */
434 #define BF_FTM_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MOD_MOD) & BM_FTM_MOD_MOD)
436 /*! @brief Set the MOD field to a new value. */
437 #define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v)))
440 /*******************************************************************************
441 * HW_FTM_CnSC - Channel (n) Status And Control
442 ******************************************************************************/
445 * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
447 * Reset value: 0x00000000U
449 * CnSC contains the channel-interrupt-status flag and control bits used to
450 * configure the interrupt enable, channel configuration, and pin function. Mode,
451 * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
452 * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
453 * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
454 * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
455 * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
456 * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
457 * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
458 * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
459 * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
460 * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
461 * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
462 * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
463 * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
464 * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
465 * Enabled Rising and falling edges
467 typedef union _hw_ftm_cnsc
470 struct _hw_ftm_cnsc_bitfields
472 uint32_t DMA : 1; /*!< [0] DMA Enable */
473 uint32_t RESERVED0 : 1; /*!< [1] */
474 uint32_t ELSA : 1; /*!< [2] Edge or Level Select */
475 uint32_t ELSB : 1; /*!< [3] Edge or Level Select */
476 uint32_t MSA : 1; /*!< [4] Channel Mode Select */
477 uint32_t MSB : 1; /*!< [5] Channel Mode Select */
478 uint32_t CHIE : 1; /*!< [6] Channel Interrupt Enable */
479 uint32_t CHF : 1; /*!< [7] Channel Flag */
480 uint32_t RESERVED1 : 24; /*!< [31:8] */
485 * @name Constants and macros for entire FTM_CnSC register
488 #define HW_FTM_CnSC_COUNT (8U)
490 #define HW_FTM_CnSC_ADDR(x, n) ((x) + 0xCU + (0x8U * (n)))
492 #define HW_FTM_CnSC(x, n) (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n))
493 #define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U)
494 #define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v))
495 #define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) | (v)))
496 #define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
497 #define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v)))
501 * Constants & macros for individual FTM_CnSC bitfields
505 * @name Register FTM_CnSC, field DMA[0] (RW)
507 * Enables DMA transfers for the channel.
510 * - 0 - Disable DMA transfers.
511 * - 1 - Enable DMA transfers.
514 #define BP_FTM_CnSC_DMA (0U) /*!< Bit position for FTM_CnSC_DMA. */
515 #define BM_FTM_CnSC_DMA (0x00000001U) /*!< Bit mask for FTM_CnSC_DMA. */
516 #define BS_FTM_CnSC_DMA (1U) /*!< Bit field size in bits for FTM_CnSC_DMA. */
518 /*! @brief Read current value of the FTM_CnSC_DMA field. */
519 #define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
521 /*! @brief Format value for bitfield FTM_CnSC_DMA. */
522 #define BF_FTM_CnSC_DMA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_DMA) & BM_FTM_CnSC_DMA)
524 /*! @brief Set the DMA field to a new value. */
525 #define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
529 * @name Register FTM_CnSC, field ELSA[2] (RW)
531 * The functionality of ELSB and ELSA depends on the channel mode. See
532 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
536 #define BP_FTM_CnSC_ELSA (2U) /*!< Bit position for FTM_CnSC_ELSA. */
537 #define BM_FTM_CnSC_ELSA (0x00000004U) /*!< Bit mask for FTM_CnSC_ELSA. */
538 #define BS_FTM_CnSC_ELSA (1U) /*!< Bit field size in bits for FTM_CnSC_ELSA. */
540 /*! @brief Read current value of the FTM_CnSC_ELSA field. */
541 #define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
543 /*! @brief Format value for bitfield FTM_CnSC_ELSA. */
544 #define BF_FTM_CnSC_ELSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSA) & BM_FTM_CnSC_ELSA)
546 /*! @brief Set the ELSA field to a new value. */
547 #define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
551 * @name Register FTM_CnSC, field ELSB[3] (RW)
553 * The functionality of ELSB and ELSA depends on the channel mode. See
554 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
558 #define BP_FTM_CnSC_ELSB (3U) /*!< Bit position for FTM_CnSC_ELSB. */
559 #define BM_FTM_CnSC_ELSB (0x00000008U) /*!< Bit mask for FTM_CnSC_ELSB. */
560 #define BS_FTM_CnSC_ELSB (1U) /*!< Bit field size in bits for FTM_CnSC_ELSB. */
562 /*! @brief Read current value of the FTM_CnSC_ELSB field. */
563 #define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
565 /*! @brief Format value for bitfield FTM_CnSC_ELSB. */
566 #define BF_FTM_CnSC_ELSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSB) & BM_FTM_CnSC_ELSB)
568 /*! @brief Set the ELSB field to a new value. */
569 #define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
573 * @name Register FTM_CnSC, field MSA[4] (RW)
575 * Used for further selections in the channel logic. Its functionality is
576 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
577 * can be written only when MODE[WPDIS] = 1.
580 #define BP_FTM_CnSC_MSA (4U) /*!< Bit position for FTM_CnSC_MSA. */
581 #define BM_FTM_CnSC_MSA (0x00000010U) /*!< Bit mask for FTM_CnSC_MSA. */
582 #define BS_FTM_CnSC_MSA (1U) /*!< Bit field size in bits for FTM_CnSC_MSA. */
584 /*! @brief Read current value of the FTM_CnSC_MSA field. */
585 #define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
587 /*! @brief Format value for bitfield FTM_CnSC_MSA. */
588 #define BF_FTM_CnSC_MSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSA) & BM_FTM_CnSC_MSA)
590 /*! @brief Set the MSA field to a new value. */
591 #define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
595 * @name Register FTM_CnSC, field MSB[5] (RW)
597 * Used for further selections in the channel logic. Its functionality is
598 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
599 * can be written only when MODE[WPDIS] = 1.
602 #define BP_FTM_CnSC_MSB (5U) /*!< Bit position for FTM_CnSC_MSB. */
603 #define BM_FTM_CnSC_MSB (0x00000020U) /*!< Bit mask for FTM_CnSC_MSB. */
604 #define BS_FTM_CnSC_MSB (1U) /*!< Bit field size in bits for FTM_CnSC_MSB. */
606 /*! @brief Read current value of the FTM_CnSC_MSB field. */
607 #define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
609 /*! @brief Format value for bitfield FTM_CnSC_MSB. */
610 #define BF_FTM_CnSC_MSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSB) & BM_FTM_CnSC_MSB)
612 /*! @brief Set the MSB field to a new value. */
613 #define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
617 * @name Register FTM_CnSC, field CHIE[6] (RW)
619 * Enables channel interrupts.
622 * - 0 - Disable channel interrupts. Use software polling.
623 * - 1 - Enable channel interrupts.
626 #define BP_FTM_CnSC_CHIE (6U) /*!< Bit position for FTM_CnSC_CHIE. */
627 #define BM_FTM_CnSC_CHIE (0x00000040U) /*!< Bit mask for FTM_CnSC_CHIE. */
628 #define BS_FTM_CnSC_CHIE (1U) /*!< Bit field size in bits for FTM_CnSC_CHIE. */
630 /*! @brief Read current value of the FTM_CnSC_CHIE field. */
631 #define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
633 /*! @brief Format value for bitfield FTM_CnSC_CHIE. */
634 #define BF_FTM_CnSC_CHIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHIE) & BM_FTM_CnSC_CHIE)
636 /*! @brief Set the CHIE field to a new value. */
637 #define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
641 * @name Register FTM_CnSC, field CHF[7] (ROWZ)
643 * Set by hardware when an event occurs on the channel. CHF is cleared by
644 * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
645 * Writing a 1 to CHF has no effect. If another event occurs between the read and
646 * write operations, the write operation has no effect; therefore, CHF remains set
647 * indicating an event has occurred. In this case a CHF interrupt request is not
648 * lost due to the clearing sequence for a previous CHF.
651 * - 0 - No channel event has occurred.
652 * - 1 - A channel event has occurred.
655 #define BP_FTM_CnSC_CHF (7U) /*!< Bit position for FTM_CnSC_CHF. */
656 #define BM_FTM_CnSC_CHF (0x00000080U) /*!< Bit mask for FTM_CnSC_CHF. */
657 #define BS_FTM_CnSC_CHF (1U) /*!< Bit field size in bits for FTM_CnSC_CHF. */
659 /*! @brief Read current value of the FTM_CnSC_CHF field. */
660 #define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
662 /*! @brief Format value for bitfield FTM_CnSC_CHF. */
663 #define BF_FTM_CnSC_CHF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHF) & BM_FTM_CnSC_CHF)
665 /*! @brief Set the CHF field to a new value. */
666 #define BW_FTM_CnSC_CHF(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF) = (v))
668 /*******************************************************************************
669 * HW_FTM_CnV - Channel (n) Value
670 ******************************************************************************/
673 * @brief HW_FTM_CnV - Channel (n) Value (RW)
675 * Reset value: 0x00000000U
677 * These registers contain the captured FTM counter value for the input modes or
678 * the match value for the output modes. In Input Capture, Capture Test, and
679 * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
680 * writing to a CnV register latches the value into a buffer. A CnV register is
681 * updated with the value of its write buffer according to Registers updated from
682 * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
683 * reset by writing to the CnSC register whether BDM mode is active or not.
685 typedef union _hw_ftm_cnv
688 struct _hw_ftm_cnv_bitfields
690 uint32_t VAL : 16; /*!< [15:0] Channel Value */
691 uint32_t RESERVED0 : 16; /*!< [31:16] */
696 * @name Constants and macros for entire FTM_CnV register
699 #define HW_FTM_CnV_COUNT (8U)
701 #define HW_FTM_CnV_ADDR(x, n) ((x) + 0x10U + (0x8U * (n)))
703 #define HW_FTM_CnV(x, n) (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n))
704 #define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U)
705 #define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v))
706 #define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) | (v)))
707 #define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
708 #define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v)))
712 * Constants & macros for individual FTM_CnV bitfields
716 * @name Register FTM_CnV, field VAL[15:0] (RW)
718 * Captured FTM counter value of the input modes or the match value for the
722 #define BP_FTM_CnV_VAL (0U) /*!< Bit position for FTM_CnV_VAL. */
723 #define BM_FTM_CnV_VAL (0x0000FFFFU) /*!< Bit mask for FTM_CnV_VAL. */
724 #define BS_FTM_CnV_VAL (16U) /*!< Bit field size in bits for FTM_CnV_VAL. */
726 /*! @brief Read current value of the FTM_CnV_VAL field. */
727 #define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
729 /*! @brief Format value for bitfield FTM_CnV_VAL. */
730 #define BF_FTM_CnV_VAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnV_VAL) & BM_FTM_CnV_VAL)
732 /*! @brief Set the VAL field to a new value. */
733 #define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v)))
736 /*******************************************************************************
737 * HW_FTM_CNTIN - Counter Initial Value
738 ******************************************************************************/
741 * @brief HW_FTM_CNTIN - Counter Initial Value (RW)
743 * Reset value: 0x00000000U
745 * The Counter Initial Value register contains the initial value for the FTM
746 * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
747 * register is updated with the value of its write buffer according to Registers
748 * updated from write buffers. When the FTM clock is initially selected, by
749 * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
750 * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
751 * write the new value to the the CNTIN register and then initialize the FTM
752 * counter by writing any value to the CNT register.
754 typedef union _hw_ftm_cntin
757 struct _hw_ftm_cntin_bitfields
759 uint32_t INIT : 16; /*!< [15:0] */
760 uint32_t RESERVED0 : 16; /*!< [31:16] */
765 * @name Constants and macros for entire FTM_CNTIN register
768 #define HW_FTM_CNTIN_ADDR(x) ((x) + 0x4CU)
770 #define HW_FTM_CNTIN(x) (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x))
771 #define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U)
772 #define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v))
773 #define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) | (v)))
774 #define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
775 #define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v)))
779 * Constants & macros for individual FTM_CNTIN bitfields
783 * @name Register FTM_CNTIN, field INIT[15:0] (RW)
785 * Initial Value Of The FTM Counter
788 #define BP_FTM_CNTIN_INIT (0U) /*!< Bit position for FTM_CNTIN_INIT. */
789 #define BM_FTM_CNTIN_INIT (0x0000FFFFU) /*!< Bit mask for FTM_CNTIN_INIT. */
790 #define BS_FTM_CNTIN_INIT (16U) /*!< Bit field size in bits for FTM_CNTIN_INIT. */
792 /*! @brief Read current value of the FTM_CNTIN_INIT field. */
793 #define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
795 /*! @brief Format value for bitfield FTM_CNTIN_INIT. */
796 #define BF_FTM_CNTIN_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNTIN_INIT) & BM_FTM_CNTIN_INIT)
798 /*! @brief Set the INIT field to a new value. */
799 #define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v)))
802 /*******************************************************************************
803 * HW_FTM_STATUS - Capture And Compare Status
804 ******************************************************************************/
807 * @brief HW_FTM_STATUS - Capture And Compare Status (RW)
809 * Reset value: 0x00000000U
811 * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
812 * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
813 * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
814 * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
815 * STATUS. Hardware sets the individual channel flags when an event occurs on the
816 * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
817 * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
818 * occurs between the read and write operations, the write operation has no effect;
819 * therefore, CHnF remains set indicating an event has occurred. In this case, a
820 * CHnF interrupt request is not lost due to the clearing sequence for a previous
821 * CHnF. The STATUS register should be used only in Combine mode.
823 typedef union _hw_ftm_status
826 struct _hw_ftm_status_bitfields
828 uint32_t CH0F : 1; /*!< [0] Channel 0 Flag */
829 uint32_t CH1F : 1; /*!< [1] Channel 1 Flag */
830 uint32_t CH2F : 1; /*!< [2] Channel 2 Flag */
831 uint32_t CH3F : 1; /*!< [3] Channel 3 Flag */
832 uint32_t CH4F : 1; /*!< [4] Channel 4 Flag */
833 uint32_t CH5F : 1; /*!< [5] Channel 5 Flag */
834 uint32_t CH6F : 1; /*!< [6] Channel 6 Flag */
835 uint32_t CH7F : 1; /*!< [7] Channel 7 Flag */
836 uint32_t RESERVED0 : 24; /*!< [31:8] */
841 * @name Constants and macros for entire FTM_STATUS register
844 #define HW_FTM_STATUS_ADDR(x) ((x) + 0x50U)
846 #define HW_FTM_STATUS(x) (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x))
847 #define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U)
848 #define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v))
849 #define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) | (v)))
850 #define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
851 #define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v)))
855 * Constants & macros for individual FTM_STATUS bitfields
859 * @name Register FTM_STATUS, field CH0F[0] (W1C)
861 * See the register description.
864 * - 0 - No channel event has occurred.
865 * - 1 - A channel event has occurred.
868 #define BP_FTM_STATUS_CH0F (0U) /*!< Bit position for FTM_STATUS_CH0F. */
869 #define BM_FTM_STATUS_CH0F (0x00000001U) /*!< Bit mask for FTM_STATUS_CH0F. */
870 #define BS_FTM_STATUS_CH0F (1U) /*!< Bit field size in bits for FTM_STATUS_CH0F. */
872 /*! @brief Read current value of the FTM_STATUS_CH0F field. */
873 #define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
875 /*! @brief Format value for bitfield FTM_STATUS_CH0F. */
876 #define BF_FTM_STATUS_CH0F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH0F) & BM_FTM_STATUS_CH0F)
878 /*! @brief Set the CH0F field to a new value. */
879 #define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
883 * @name Register FTM_STATUS, field CH1F[1] (W1C)
885 * See the register description.
888 * - 0 - No channel event has occurred.
889 * - 1 - A channel event has occurred.
892 #define BP_FTM_STATUS_CH1F (1U) /*!< Bit position for FTM_STATUS_CH1F. */
893 #define BM_FTM_STATUS_CH1F (0x00000002U) /*!< Bit mask for FTM_STATUS_CH1F. */
894 #define BS_FTM_STATUS_CH1F (1U) /*!< Bit field size in bits for FTM_STATUS_CH1F. */
896 /*! @brief Read current value of the FTM_STATUS_CH1F field. */
897 #define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
899 /*! @brief Format value for bitfield FTM_STATUS_CH1F. */
900 #define BF_FTM_STATUS_CH1F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH1F) & BM_FTM_STATUS_CH1F)
902 /*! @brief Set the CH1F field to a new value. */
903 #define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
907 * @name Register FTM_STATUS, field CH2F[2] (W1C)
909 * See the register description.
912 * - 0 - No channel event has occurred.
913 * - 1 - A channel event has occurred.
916 #define BP_FTM_STATUS_CH2F (2U) /*!< Bit position for FTM_STATUS_CH2F. */
917 #define BM_FTM_STATUS_CH2F (0x00000004U) /*!< Bit mask for FTM_STATUS_CH2F. */
918 #define BS_FTM_STATUS_CH2F (1U) /*!< Bit field size in bits for FTM_STATUS_CH2F. */
920 /*! @brief Read current value of the FTM_STATUS_CH2F field. */
921 #define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
923 /*! @brief Format value for bitfield FTM_STATUS_CH2F. */
924 #define BF_FTM_STATUS_CH2F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH2F) & BM_FTM_STATUS_CH2F)
926 /*! @brief Set the CH2F field to a new value. */
927 #define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
931 * @name Register FTM_STATUS, field CH3F[3] (W1C)
933 * See the register description.
936 * - 0 - No channel event has occurred.
937 * - 1 - A channel event has occurred.
940 #define BP_FTM_STATUS_CH3F (3U) /*!< Bit position for FTM_STATUS_CH3F. */
941 #define BM_FTM_STATUS_CH3F (0x00000008U) /*!< Bit mask for FTM_STATUS_CH3F. */
942 #define BS_FTM_STATUS_CH3F (1U) /*!< Bit field size in bits for FTM_STATUS_CH3F. */
944 /*! @brief Read current value of the FTM_STATUS_CH3F field. */
945 #define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
947 /*! @brief Format value for bitfield FTM_STATUS_CH3F. */
948 #define BF_FTM_STATUS_CH3F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH3F) & BM_FTM_STATUS_CH3F)
950 /*! @brief Set the CH3F field to a new value. */
951 #define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
955 * @name Register FTM_STATUS, field CH4F[4] (W1C)
957 * See the register description.
960 * - 0 - No channel event has occurred.
961 * - 1 - A channel event has occurred.
964 #define BP_FTM_STATUS_CH4F (4U) /*!< Bit position for FTM_STATUS_CH4F. */
965 #define BM_FTM_STATUS_CH4F (0x00000010U) /*!< Bit mask for FTM_STATUS_CH4F. */
966 #define BS_FTM_STATUS_CH4F (1U) /*!< Bit field size in bits for FTM_STATUS_CH4F. */
968 /*! @brief Read current value of the FTM_STATUS_CH4F field. */
969 #define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
971 /*! @brief Format value for bitfield FTM_STATUS_CH4F. */
972 #define BF_FTM_STATUS_CH4F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH4F) & BM_FTM_STATUS_CH4F)
974 /*! @brief Set the CH4F field to a new value. */
975 #define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
979 * @name Register FTM_STATUS, field CH5F[5] (W1C)
981 * See the register description.
984 * - 0 - No channel event has occurred.
985 * - 1 - A channel event has occurred.
988 #define BP_FTM_STATUS_CH5F (5U) /*!< Bit position for FTM_STATUS_CH5F. */
989 #define BM_FTM_STATUS_CH5F (0x00000020U) /*!< Bit mask for FTM_STATUS_CH5F. */
990 #define BS_FTM_STATUS_CH5F (1U) /*!< Bit field size in bits for FTM_STATUS_CH5F. */
992 /*! @brief Read current value of the FTM_STATUS_CH5F field. */
993 #define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
995 /*! @brief Format value for bitfield FTM_STATUS_CH5F. */
996 #define BF_FTM_STATUS_CH5F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH5F) & BM_FTM_STATUS_CH5F)
998 /*! @brief Set the CH5F field to a new value. */
999 #define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
1003 * @name Register FTM_STATUS, field CH6F[6] (W1C)
1005 * See the register description.
1008 * - 0 - No channel event has occurred.
1009 * - 1 - A channel event has occurred.
1012 #define BP_FTM_STATUS_CH6F (6U) /*!< Bit position for FTM_STATUS_CH6F. */
1013 #define BM_FTM_STATUS_CH6F (0x00000040U) /*!< Bit mask for FTM_STATUS_CH6F. */
1014 #define BS_FTM_STATUS_CH6F (1U) /*!< Bit field size in bits for FTM_STATUS_CH6F. */
1016 /*! @brief Read current value of the FTM_STATUS_CH6F field. */
1017 #define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
1019 /*! @brief Format value for bitfield FTM_STATUS_CH6F. */
1020 #define BF_FTM_STATUS_CH6F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH6F) & BM_FTM_STATUS_CH6F)
1022 /*! @brief Set the CH6F field to a new value. */
1023 #define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
1027 * @name Register FTM_STATUS, field CH7F[7] (W1C)
1029 * See the register description.
1032 * - 0 - No channel event has occurred.
1033 * - 1 - A channel event has occurred.
1036 #define BP_FTM_STATUS_CH7F (7U) /*!< Bit position for FTM_STATUS_CH7F. */
1037 #define BM_FTM_STATUS_CH7F (0x00000080U) /*!< Bit mask for FTM_STATUS_CH7F. */
1038 #define BS_FTM_STATUS_CH7F (1U) /*!< Bit field size in bits for FTM_STATUS_CH7F. */
1040 /*! @brief Read current value of the FTM_STATUS_CH7F field. */
1041 #define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
1043 /*! @brief Format value for bitfield FTM_STATUS_CH7F. */
1044 #define BF_FTM_STATUS_CH7F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH7F) & BM_FTM_STATUS_CH7F)
1046 /*! @brief Set the CH7F field to a new value. */
1047 #define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
1050 /*******************************************************************************
1051 * HW_FTM_MODE - Features Mode Selection
1052 ******************************************************************************/
1055 * @brief HW_FTM_MODE - Features Mode Selection (RW)
1057 * Reset value: 0x00000004U
1059 * This register contains the global enable bit for FTM-specific features and
1060 * the control bits used to configure: Fault control mode and interrupt Capture
1061 * Test mode PWM synchronization Write protection Channel output initialization
1062 * These controls relate to all channels within this module.
1064 typedef union _hw_ftm_mode
1067 struct _hw_ftm_mode_bitfields
1069 uint32_t FTMEN : 1; /*!< [0] FTM Enable */
1070 uint32_t INIT : 1; /*!< [1] Initialize The Channels Output */
1071 uint32_t WPDIS : 1; /*!< [2] Write Protection Disable */
1072 uint32_t PWMSYNC : 1; /*!< [3] PWM Synchronization Mode */
1073 uint32_t CAPTEST : 1; /*!< [4] Capture Test Mode Enable */
1074 uint32_t FAULTM : 2; /*!< [6:5] Fault Control Mode */
1075 uint32_t FAULTIE : 1; /*!< [7] Fault Interrupt Enable */
1076 uint32_t RESERVED0 : 24; /*!< [31:8] */
1081 * @name Constants and macros for entire FTM_MODE register
1084 #define HW_FTM_MODE_ADDR(x) ((x) + 0x54U)
1086 #define HW_FTM_MODE(x) (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x))
1087 #define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U)
1088 #define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v))
1089 #define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) | (v)))
1090 #define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
1091 #define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v)))
1095 * Constants & macros for individual FTM_MODE bitfields
1099 * @name Register FTM_MODE, field FTMEN[0] (RW)
1101 * This field is write protected. It can be written only when MODE[WPDIS] = 1.
1104 * - 0 - Only the TPM-compatible registers (first set of registers) can be used
1105 * without any restriction. Do not use the FTM-specific registers.
1106 * - 1 - All registers including the FTM-specific registers (second set of
1107 * registers) are available for use with no restrictions.
1110 #define BP_FTM_MODE_FTMEN (0U) /*!< Bit position for FTM_MODE_FTMEN. */
1111 #define BM_FTM_MODE_FTMEN (0x00000001U) /*!< Bit mask for FTM_MODE_FTMEN. */
1112 #define BS_FTM_MODE_FTMEN (1U) /*!< Bit field size in bits for FTM_MODE_FTMEN. */
1114 /*! @brief Read current value of the FTM_MODE_FTMEN field. */
1115 #define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
1117 /*! @brief Format value for bitfield FTM_MODE_FTMEN. */
1118 #define BF_FTM_MODE_FTMEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FTMEN) & BM_FTM_MODE_FTMEN)
1120 /*! @brief Set the FTMEN field to a new value. */
1121 #define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
1125 * @name Register FTM_MODE, field INIT[1] (RW)
1127 * When a 1 is written to INIT bit the channels output is initialized according
1128 * to the state of their corresponding bit in the OUTINIT register. Writing a 0
1129 * to INIT bit has no effect. The INIT bit is always read as 0.
1132 #define BP_FTM_MODE_INIT (1U) /*!< Bit position for FTM_MODE_INIT. */
1133 #define BM_FTM_MODE_INIT (0x00000002U) /*!< Bit mask for FTM_MODE_INIT. */
1134 #define BS_FTM_MODE_INIT (1U) /*!< Bit field size in bits for FTM_MODE_INIT. */
1136 /*! @brief Read current value of the FTM_MODE_INIT field. */
1137 #define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
1139 /*! @brief Format value for bitfield FTM_MODE_INIT. */
1140 #define BF_FTM_MODE_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_INIT) & BM_FTM_MODE_INIT)
1142 /*! @brief Set the INIT field to a new value. */
1143 #define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
1147 * @name Register FTM_MODE, field WPDIS[2] (RW)
1149 * When write protection is enabled (WPDIS = 0), write protected bits cannot be
1150 * written. When write protection is disabled (WPDIS = 1), write protected bits
1151 * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
1152 * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
1153 * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
1156 * - 0 - Write protection is enabled.
1157 * - 1 - Write protection is disabled.
1160 #define BP_FTM_MODE_WPDIS (2U) /*!< Bit position for FTM_MODE_WPDIS. */
1161 #define BM_FTM_MODE_WPDIS (0x00000004U) /*!< Bit mask for FTM_MODE_WPDIS. */
1162 #define BS_FTM_MODE_WPDIS (1U) /*!< Bit field size in bits for FTM_MODE_WPDIS. */
1164 /*! @brief Read current value of the FTM_MODE_WPDIS field. */
1165 #define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
1167 /*! @brief Format value for bitfield FTM_MODE_WPDIS. */
1168 #define BF_FTM_MODE_WPDIS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_WPDIS) & BM_FTM_MODE_WPDIS)
1170 /*! @brief Set the WPDIS field to a new value. */
1171 #define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
1175 * @name Register FTM_MODE, field PWMSYNC[3] (RW)
1177 * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
1178 * synchronization. See PWM synchronization. The PWMSYNC bit configures the
1179 * synchronization when SYNCMODE is 0.
1182 * - 0 - No restrictions. Software and hardware triggers can be used by MOD,
1183 * CnV, OUTMASK, and FTM counter synchronization.
1184 * - 1 - Software trigger can only be used by MOD and CnV synchronization, and
1185 * hardware triggers can only be used by OUTMASK and FTM counter
1189 #define BP_FTM_MODE_PWMSYNC (3U) /*!< Bit position for FTM_MODE_PWMSYNC. */
1190 #define BM_FTM_MODE_PWMSYNC (0x00000008U) /*!< Bit mask for FTM_MODE_PWMSYNC. */
1191 #define BS_FTM_MODE_PWMSYNC (1U) /*!< Bit field size in bits for FTM_MODE_PWMSYNC. */
1193 /*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
1194 #define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
1196 /*! @brief Format value for bitfield FTM_MODE_PWMSYNC. */
1197 #define BF_FTM_MODE_PWMSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_PWMSYNC) & BM_FTM_MODE_PWMSYNC)
1199 /*! @brief Set the PWMSYNC field to a new value. */
1200 #define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
1204 * @name Register FTM_MODE, field CAPTEST[4] (RW)
1206 * Enables the capture test mode. This field is write protected. It can be
1207 * written only when MODE[WPDIS] = 1.
1210 * - 0 - Capture test mode is disabled.
1211 * - 1 - Capture test mode is enabled.
1214 #define BP_FTM_MODE_CAPTEST (4U) /*!< Bit position for FTM_MODE_CAPTEST. */
1215 #define BM_FTM_MODE_CAPTEST (0x00000010U) /*!< Bit mask for FTM_MODE_CAPTEST. */
1216 #define BS_FTM_MODE_CAPTEST (1U) /*!< Bit field size in bits for FTM_MODE_CAPTEST. */
1218 /*! @brief Read current value of the FTM_MODE_CAPTEST field. */
1219 #define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
1221 /*! @brief Format value for bitfield FTM_MODE_CAPTEST. */
1222 #define BF_FTM_MODE_CAPTEST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_CAPTEST) & BM_FTM_MODE_CAPTEST)
1224 /*! @brief Set the CAPTEST field to a new value. */
1225 #define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
1229 * @name Register FTM_MODE, field FAULTM[6:5] (RW)
1231 * Defines the FTM fault control mode. This field is write protected. It can be
1232 * written only when MODE[WPDIS] = 1.
1235 * - 00 - Fault control is disabled for all channels.
1236 * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
1237 * 6), and the selected mode is the manual fault clearing.
1238 * - 10 - Fault control is enabled for all channels, and the selected mode is
1239 * the manual fault clearing.
1240 * - 11 - Fault control is enabled for all channels, and the selected mode is
1241 * the automatic fault clearing.
1244 #define BP_FTM_MODE_FAULTM (5U) /*!< Bit position for FTM_MODE_FAULTM. */
1245 #define BM_FTM_MODE_FAULTM (0x00000060U) /*!< Bit mask for FTM_MODE_FAULTM. */
1246 #define BS_FTM_MODE_FAULTM (2U) /*!< Bit field size in bits for FTM_MODE_FAULTM. */
1248 /*! @brief Read current value of the FTM_MODE_FAULTM field. */
1249 #define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
1251 /*! @brief Format value for bitfield FTM_MODE_FAULTM. */
1252 #define BF_FTM_MODE_FAULTM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTM) & BM_FTM_MODE_FAULTM)
1254 /*! @brief Set the FAULTM field to a new value. */
1255 #define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v)))
1259 * @name Register FTM_MODE, field FAULTIE[7] (RW)
1261 * Enables the generation of an interrupt when a fault is detected by FTM and
1262 * the FTM fault control is enabled.
1265 * - 0 - Fault control interrupt is disabled.
1266 * - 1 - Fault control interrupt is enabled.
1269 #define BP_FTM_MODE_FAULTIE (7U) /*!< Bit position for FTM_MODE_FAULTIE. */
1270 #define BM_FTM_MODE_FAULTIE (0x00000080U) /*!< Bit mask for FTM_MODE_FAULTIE. */
1271 #define BS_FTM_MODE_FAULTIE (1U) /*!< Bit field size in bits for FTM_MODE_FAULTIE. */
1273 /*! @brief Read current value of the FTM_MODE_FAULTIE field. */
1274 #define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
1276 /*! @brief Format value for bitfield FTM_MODE_FAULTIE. */
1277 #define BF_FTM_MODE_FAULTIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTIE) & BM_FTM_MODE_FAULTIE)
1279 /*! @brief Set the FAULTIE field to a new value. */
1280 #define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
1283 /*******************************************************************************
1284 * HW_FTM_SYNC - Synchronization
1285 ******************************************************************************/
1288 * @brief HW_FTM_SYNC - Synchronization (RW)
1290 * Reset value: 0x00000000U
1292 * This register configures the PWM synchronization. A synchronization event can
1293 * perform the synchronized update of MOD, CV, and OUTMASK registers with the
1294 * value of their write buffer and the FTM counter initialization. The software
1295 * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
1296 * potential conflict if used together when SYNCMODE = 0. Use only hardware or
1297 * software triggers but not both at the same time, otherwise unpredictable behavior
1298 * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
1299 * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
1300 * all enabled channels simultaneously. The use of the loading point selection
1301 * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
1302 * bits, is likely to result in unpredictable behavior. The synchronization
1303 * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
1304 * register) bits. See PWM synchronization.
1306 typedef union _hw_ftm_sync
1309 struct _hw_ftm_sync_bitfields
1311 uint32_t CNTMIN : 1; /*!< [0] Minimum Loading Point Enable */
1312 uint32_t CNTMAX : 1; /*!< [1] Maximum Loading Point Enable */
1313 uint32_t REINIT : 1; /*!< [2] FTM Counter Reinitialization By
1314 * Synchronization (FTM counter synchronization) */
1315 uint32_t SYNCHOM : 1; /*!< [3] Output Mask Synchronization */
1316 uint32_t TRIG0 : 1; /*!< [4] PWM Synchronization Hardware Trigger 0 */
1317 uint32_t TRIG1 : 1; /*!< [5] PWM Synchronization Hardware Trigger 1 */
1318 uint32_t TRIG2 : 1; /*!< [6] PWM Synchronization Hardware Trigger 2 */
1319 uint32_t SWSYNC : 1; /*!< [7] PWM Synchronization Software Trigger */
1320 uint32_t RESERVED0 : 24; /*!< [31:8] */
1325 * @name Constants and macros for entire FTM_SYNC register
1328 #define HW_FTM_SYNC_ADDR(x) ((x) + 0x58U)
1330 #define HW_FTM_SYNC(x) (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x))
1331 #define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U)
1332 #define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v))
1333 #define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) | (v)))
1334 #define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
1335 #define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v)))
1339 * Constants & macros for individual FTM_SYNC bitfields
1343 * @name Register FTM_SYNC, field CNTMIN[0] (RW)
1345 * Selects the minimum loading point to PWM synchronization. See Boundary cycle
1346 * and loading points. If CNTMIN is one, the selected loading point is when the
1347 * FTM counter reaches its minimum value (CNTIN register).
1350 * - 0 - The minimum loading point is disabled.
1351 * - 1 - The minimum loading point is enabled.
1354 #define BP_FTM_SYNC_CNTMIN (0U) /*!< Bit position for FTM_SYNC_CNTMIN. */
1355 #define BM_FTM_SYNC_CNTMIN (0x00000001U) /*!< Bit mask for FTM_SYNC_CNTMIN. */
1356 #define BS_FTM_SYNC_CNTMIN (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMIN. */
1358 /*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
1359 #define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
1361 /*! @brief Format value for bitfield FTM_SYNC_CNTMIN. */
1362 #define BF_FTM_SYNC_CNTMIN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMIN) & BM_FTM_SYNC_CNTMIN)
1364 /*! @brief Set the CNTMIN field to a new value. */
1365 #define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
1369 * @name Register FTM_SYNC, field CNTMAX[1] (RW)
1371 * Selects the maximum loading point to PWM synchronization. See Boundary cycle
1372 * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
1373 * counter reaches its maximum value (MOD register).
1376 * - 0 - The maximum loading point is disabled.
1377 * - 1 - The maximum loading point is enabled.
1380 #define BP_FTM_SYNC_CNTMAX (1U) /*!< Bit position for FTM_SYNC_CNTMAX. */
1381 #define BM_FTM_SYNC_CNTMAX (0x00000002U) /*!< Bit mask for FTM_SYNC_CNTMAX. */
1382 #define BS_FTM_SYNC_CNTMAX (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMAX. */
1384 /*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
1385 #define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
1387 /*! @brief Format value for bitfield FTM_SYNC_CNTMAX. */
1388 #define BF_FTM_SYNC_CNTMAX(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMAX) & BM_FTM_SYNC_CNTMAX)
1390 /*! @brief Set the CNTMAX field to a new value. */
1391 #define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
1395 * @name Register FTM_SYNC, field REINIT[2] (RW)
1397 * Determines if the FTM counter is reinitialized when the selected trigger for
1398 * the synchronization is detected. The REINIT bit configures the synchronization
1399 * when SYNCMODE is zero.
1402 * - 0 - FTM counter continues to count normally.
1403 * - 1 - FTM counter is updated with its initial value when the selected trigger
1407 #define BP_FTM_SYNC_REINIT (2U) /*!< Bit position for FTM_SYNC_REINIT. */
1408 #define BM_FTM_SYNC_REINIT (0x00000004U) /*!< Bit mask for FTM_SYNC_REINIT. */
1409 #define BS_FTM_SYNC_REINIT (1U) /*!< Bit field size in bits for FTM_SYNC_REINIT. */
1411 /*! @brief Read current value of the FTM_SYNC_REINIT field. */
1412 #define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
1414 /*! @brief Format value for bitfield FTM_SYNC_REINIT. */
1415 #define BF_FTM_SYNC_REINIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_REINIT) & BM_FTM_SYNC_REINIT)
1417 /*! @brief Set the REINIT field to a new value. */
1418 #define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
1422 * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
1424 * Selects when the OUTMASK register is updated with the value of its buffer.
1427 * - 0 - OUTMASK register is updated with the value of its buffer in all rising
1428 * edges of the system clock.
1429 * - 1 - OUTMASK register is updated with the value of its buffer only by the
1430 * PWM synchronization.
1433 #define BP_FTM_SYNC_SYNCHOM (3U) /*!< Bit position for FTM_SYNC_SYNCHOM. */
1434 #define BM_FTM_SYNC_SYNCHOM (0x00000008U) /*!< Bit mask for FTM_SYNC_SYNCHOM. */
1435 #define BS_FTM_SYNC_SYNCHOM (1U) /*!< Bit field size in bits for FTM_SYNC_SYNCHOM. */
1437 /*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
1438 #define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
1440 /*! @brief Format value for bitfield FTM_SYNC_SYNCHOM. */
1441 #define BF_FTM_SYNC_SYNCHOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SYNCHOM) & BM_FTM_SYNC_SYNCHOM)
1443 /*! @brief Set the SYNCHOM field to a new value. */
1444 #define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
1448 * @name Register FTM_SYNC, field TRIG0[4] (RW)
1450 * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
1451 * occurs when a rising edge is detected at the trigger 0 input signal.
1454 * - 0 - Trigger is disabled.
1455 * - 1 - Trigger is enabled.
1458 #define BP_FTM_SYNC_TRIG0 (4U) /*!< Bit position for FTM_SYNC_TRIG0. */
1459 #define BM_FTM_SYNC_TRIG0 (0x00000010U) /*!< Bit mask for FTM_SYNC_TRIG0. */
1460 #define BS_FTM_SYNC_TRIG0 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG0. */
1462 /*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
1463 #define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
1465 /*! @brief Format value for bitfield FTM_SYNC_TRIG0. */
1466 #define BF_FTM_SYNC_TRIG0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG0) & BM_FTM_SYNC_TRIG0)
1468 /*! @brief Set the TRIG0 field to a new value. */
1469 #define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
1473 * @name Register FTM_SYNC, field TRIG1[5] (RW)
1475 * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
1476 * happens when a rising edge is detected at the trigger 1 input signal.
1479 * - 0 - Trigger is disabled.
1480 * - 1 - Trigger is enabled.
1483 #define BP_FTM_SYNC_TRIG1 (5U) /*!< Bit position for FTM_SYNC_TRIG1. */
1484 #define BM_FTM_SYNC_TRIG1 (0x00000020U) /*!< Bit mask for FTM_SYNC_TRIG1. */
1485 #define BS_FTM_SYNC_TRIG1 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG1. */
1487 /*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
1488 #define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
1490 /*! @brief Format value for bitfield FTM_SYNC_TRIG1. */
1491 #define BF_FTM_SYNC_TRIG1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG1) & BM_FTM_SYNC_TRIG1)
1493 /*! @brief Set the TRIG1 field to a new value. */
1494 #define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
1498 * @name Register FTM_SYNC, field TRIG2[6] (RW)
1500 * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
1501 * happens when a rising edge is detected at the trigger 2 input signal.
1504 * - 0 - Trigger is disabled.
1505 * - 1 - Trigger is enabled.
1508 #define BP_FTM_SYNC_TRIG2 (6U) /*!< Bit position for FTM_SYNC_TRIG2. */
1509 #define BM_FTM_SYNC_TRIG2 (0x00000040U) /*!< Bit mask for FTM_SYNC_TRIG2. */
1510 #define BS_FTM_SYNC_TRIG2 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG2. */
1512 /*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
1513 #define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
1515 /*! @brief Format value for bitfield FTM_SYNC_TRIG2. */
1516 #define BF_FTM_SYNC_TRIG2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG2) & BM_FTM_SYNC_TRIG2)
1518 /*! @brief Set the TRIG2 field to a new value. */
1519 #define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
1523 * @name Register FTM_SYNC, field SWSYNC[7] (RW)
1525 * Selects the software trigger as the PWM synchronization trigger. The software
1526 * trigger happens when a 1 is written to SWSYNC bit.
1529 * - 0 - Software trigger is not selected.
1530 * - 1 - Software trigger is selected.
1533 #define BP_FTM_SYNC_SWSYNC (7U) /*!< Bit position for FTM_SYNC_SWSYNC. */
1534 #define BM_FTM_SYNC_SWSYNC (0x00000080U) /*!< Bit mask for FTM_SYNC_SWSYNC. */
1535 #define BS_FTM_SYNC_SWSYNC (1U) /*!< Bit field size in bits for FTM_SYNC_SWSYNC. */
1537 /*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
1538 #define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
1540 /*! @brief Format value for bitfield FTM_SYNC_SWSYNC. */
1541 #define BF_FTM_SYNC_SWSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SWSYNC) & BM_FTM_SYNC_SWSYNC)
1543 /*! @brief Set the SWSYNC field to a new value. */
1544 #define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
1547 /*******************************************************************************
1548 * HW_FTM_OUTINIT - Initial State For Channels Output
1549 ******************************************************************************/
1552 * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
1554 * Reset value: 0x00000000U
1556 typedef union _hw_ftm_outinit
1559 struct _hw_ftm_outinit_bitfields
1561 uint32_t CH0OI : 1; /*!< [0] Channel 0 Output Initialization Value */
1562 uint32_t CH1OI : 1; /*!< [1] Channel 1 Output Initialization Value */
1563 uint32_t CH2OI : 1; /*!< [2] Channel 2 Output Initialization Value */
1564 uint32_t CH3OI : 1; /*!< [3] Channel 3 Output Initialization Value */
1565 uint32_t CH4OI : 1; /*!< [4] Channel 4 Output Initialization Value */
1566 uint32_t CH5OI : 1; /*!< [5] Channel 5 Output Initialization Value */
1567 uint32_t CH6OI : 1; /*!< [6] Channel 6 Output Initialization Value */
1568 uint32_t CH7OI : 1; /*!< [7] Channel 7 Output Initialization Value */
1569 uint32_t RESERVED0 : 24; /*!< [31:8] */
1574 * @name Constants and macros for entire FTM_OUTINIT register
1577 #define HW_FTM_OUTINIT_ADDR(x) ((x) + 0x5CU)
1579 #define HW_FTM_OUTINIT(x) (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x))
1580 #define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U)
1581 #define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v))
1582 #define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) | (v)))
1583 #define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
1584 #define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v)))
1588 * Constants & macros for individual FTM_OUTINIT bitfields
1592 * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
1594 * Selects the value that is forced into the channel output when the
1595 * initialization occurs.
1598 * - 0 - The initialization value is 0.
1599 * - 1 - The initialization value is 1.
1602 #define BP_FTM_OUTINIT_CH0OI (0U) /*!< Bit position for FTM_OUTINIT_CH0OI. */
1603 #define BM_FTM_OUTINIT_CH0OI (0x00000001U) /*!< Bit mask for FTM_OUTINIT_CH0OI. */
1604 #define BS_FTM_OUTINIT_CH0OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH0OI. */
1606 /*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
1607 #define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
1609 /*! @brief Format value for bitfield FTM_OUTINIT_CH0OI. */
1610 #define BF_FTM_OUTINIT_CH0OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH0OI) & BM_FTM_OUTINIT_CH0OI)
1612 /*! @brief Set the CH0OI field to a new value. */
1613 #define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
1617 * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
1619 * Selects the value that is forced into the channel output when the
1620 * initialization occurs.
1623 * - 0 - The initialization value is 0.
1624 * - 1 - The initialization value is 1.
1627 #define BP_FTM_OUTINIT_CH1OI (1U) /*!< Bit position for FTM_OUTINIT_CH1OI. */
1628 #define BM_FTM_OUTINIT_CH1OI (0x00000002U) /*!< Bit mask for FTM_OUTINIT_CH1OI. */
1629 #define BS_FTM_OUTINIT_CH1OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH1OI. */
1631 /*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
1632 #define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
1634 /*! @brief Format value for bitfield FTM_OUTINIT_CH1OI. */
1635 #define BF_FTM_OUTINIT_CH1OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH1OI) & BM_FTM_OUTINIT_CH1OI)
1637 /*! @brief Set the CH1OI field to a new value. */
1638 #define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
1642 * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
1644 * Selects the value that is forced into the channel output when the
1645 * initialization occurs.
1648 * - 0 - The initialization value is 0.
1649 * - 1 - The initialization value is 1.
1652 #define BP_FTM_OUTINIT_CH2OI (2U) /*!< Bit position for FTM_OUTINIT_CH2OI. */
1653 #define BM_FTM_OUTINIT_CH2OI (0x00000004U) /*!< Bit mask for FTM_OUTINIT_CH2OI. */
1654 #define BS_FTM_OUTINIT_CH2OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH2OI. */
1656 /*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
1657 #define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
1659 /*! @brief Format value for bitfield FTM_OUTINIT_CH2OI. */
1660 #define BF_FTM_OUTINIT_CH2OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH2OI) & BM_FTM_OUTINIT_CH2OI)
1662 /*! @brief Set the CH2OI field to a new value. */
1663 #define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
1667 * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
1669 * Selects the value that is forced into the channel output when the
1670 * initialization occurs.
1673 * - 0 - The initialization value is 0.
1674 * - 1 - The initialization value is 1.
1677 #define BP_FTM_OUTINIT_CH3OI (3U) /*!< Bit position for FTM_OUTINIT_CH3OI. */
1678 #define BM_FTM_OUTINIT_CH3OI (0x00000008U) /*!< Bit mask for FTM_OUTINIT_CH3OI. */
1679 #define BS_FTM_OUTINIT_CH3OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH3OI. */
1681 /*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
1682 #define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
1684 /*! @brief Format value for bitfield FTM_OUTINIT_CH3OI. */
1685 #define BF_FTM_OUTINIT_CH3OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH3OI) & BM_FTM_OUTINIT_CH3OI)
1687 /*! @brief Set the CH3OI field to a new value. */
1688 #define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
1692 * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
1694 * Selects the value that is forced into the channel output when the
1695 * initialization occurs.
1698 * - 0 - The initialization value is 0.
1699 * - 1 - The initialization value is 1.
1702 #define BP_FTM_OUTINIT_CH4OI (4U) /*!< Bit position for FTM_OUTINIT_CH4OI. */
1703 #define BM_FTM_OUTINIT_CH4OI (0x00000010U) /*!< Bit mask for FTM_OUTINIT_CH4OI. */
1704 #define BS_FTM_OUTINIT_CH4OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH4OI. */
1706 /*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
1707 #define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
1709 /*! @brief Format value for bitfield FTM_OUTINIT_CH4OI. */
1710 #define BF_FTM_OUTINIT_CH4OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH4OI) & BM_FTM_OUTINIT_CH4OI)
1712 /*! @brief Set the CH4OI field to a new value. */
1713 #define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
1717 * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
1719 * Selects the value that is forced into the channel output when the
1720 * initialization occurs.
1723 * - 0 - The initialization value is 0.
1724 * - 1 - The initialization value is 1.
1727 #define BP_FTM_OUTINIT_CH5OI (5U) /*!< Bit position for FTM_OUTINIT_CH5OI. */
1728 #define BM_FTM_OUTINIT_CH5OI (0x00000020U) /*!< Bit mask for FTM_OUTINIT_CH5OI. */
1729 #define BS_FTM_OUTINIT_CH5OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH5OI. */
1731 /*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
1732 #define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
1734 /*! @brief Format value for bitfield FTM_OUTINIT_CH5OI. */
1735 #define BF_FTM_OUTINIT_CH5OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH5OI) & BM_FTM_OUTINIT_CH5OI)
1737 /*! @brief Set the CH5OI field to a new value. */
1738 #define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
1742 * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
1744 * Selects the value that is forced into the channel output when the
1745 * initialization occurs.
1748 * - 0 - The initialization value is 0.
1749 * - 1 - The initialization value is 1.
1752 #define BP_FTM_OUTINIT_CH6OI (6U) /*!< Bit position for FTM_OUTINIT_CH6OI. */
1753 #define BM_FTM_OUTINIT_CH6OI (0x00000040U) /*!< Bit mask for FTM_OUTINIT_CH6OI. */
1754 #define BS_FTM_OUTINIT_CH6OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH6OI. */
1756 /*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
1757 #define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
1759 /*! @brief Format value for bitfield FTM_OUTINIT_CH6OI. */
1760 #define BF_FTM_OUTINIT_CH6OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH6OI) & BM_FTM_OUTINIT_CH6OI)
1762 /*! @brief Set the CH6OI field to a new value. */
1763 #define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
1767 * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
1769 * Selects the value that is forced into the channel output when the
1770 * initialization occurs.
1773 * - 0 - The initialization value is 0.
1774 * - 1 - The initialization value is 1.
1777 #define BP_FTM_OUTINIT_CH7OI (7U) /*!< Bit position for FTM_OUTINIT_CH7OI. */
1778 #define BM_FTM_OUTINIT_CH7OI (0x00000080U) /*!< Bit mask for FTM_OUTINIT_CH7OI. */
1779 #define BS_FTM_OUTINIT_CH7OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH7OI. */
1781 /*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
1782 #define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
1784 /*! @brief Format value for bitfield FTM_OUTINIT_CH7OI. */
1785 #define BF_FTM_OUTINIT_CH7OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH7OI) & BM_FTM_OUTINIT_CH7OI)
1787 /*! @brief Set the CH7OI field to a new value. */
1788 #define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
1791 /*******************************************************************************
1792 * HW_FTM_OUTMASK - Output Mask
1793 ******************************************************************************/
1796 * @brief HW_FTM_OUTMASK - Output Mask (RW)
1798 * Reset value: 0x00000000U
1800 * This register provides a mask for each FTM channel. The mask of a channel
1801 * determines if its output responds, that is, it is masked or not, when a match
1802 * occurs. This feature is used for BLDC control where the PWM signal is presented
1803 * to an electric motor at specific times to provide electronic commutation. Any
1804 * write to the OUTMASK register, stores the value in its write buffer. The
1805 * register is updated with the value of its write buffer according to PWM
1808 typedef union _hw_ftm_outmask
1811 struct _hw_ftm_outmask_bitfields
1813 uint32_t CH0OM : 1; /*!< [0] Channel 0 Output Mask */
1814 uint32_t CH1OM : 1; /*!< [1] Channel 1 Output Mask */
1815 uint32_t CH2OM : 1; /*!< [2] Channel 2 Output Mask */
1816 uint32_t CH3OM : 1; /*!< [3] Channel 3 Output Mask */
1817 uint32_t CH4OM : 1; /*!< [4] Channel 4 Output Mask */
1818 uint32_t CH5OM : 1; /*!< [5] Channel 5 Output Mask */
1819 uint32_t CH6OM : 1; /*!< [6] Channel 6 Output Mask */
1820 uint32_t CH7OM : 1; /*!< [7] Channel 7 Output Mask */
1821 uint32_t RESERVED0 : 24; /*!< [31:8] */
1826 * @name Constants and macros for entire FTM_OUTMASK register
1829 #define HW_FTM_OUTMASK_ADDR(x) ((x) + 0x60U)
1831 #define HW_FTM_OUTMASK(x) (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x))
1832 #define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U)
1833 #define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v))
1834 #define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) | (v)))
1835 #define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
1836 #define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v)))
1840 * Constants & macros for individual FTM_OUTMASK bitfields
1844 * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
1846 * Defines if the channel output is masked or unmasked.
1849 * - 0 - Channel output is not masked. It continues to operate normally.
1850 * - 1 - Channel output is masked. It is forced to its inactive state.
1853 #define BP_FTM_OUTMASK_CH0OM (0U) /*!< Bit position for FTM_OUTMASK_CH0OM. */
1854 #define BM_FTM_OUTMASK_CH0OM (0x00000001U) /*!< Bit mask for FTM_OUTMASK_CH0OM. */
1855 #define BS_FTM_OUTMASK_CH0OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH0OM. */
1857 /*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
1858 #define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
1860 /*! @brief Format value for bitfield FTM_OUTMASK_CH0OM. */
1861 #define BF_FTM_OUTMASK_CH0OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH0OM) & BM_FTM_OUTMASK_CH0OM)
1863 /*! @brief Set the CH0OM field to a new value. */
1864 #define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
1868 * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
1870 * Defines if the channel output is masked or unmasked.
1873 * - 0 - Channel output is not masked. It continues to operate normally.
1874 * - 1 - Channel output is masked. It is forced to its inactive state.
1877 #define BP_FTM_OUTMASK_CH1OM (1U) /*!< Bit position for FTM_OUTMASK_CH1OM. */
1878 #define BM_FTM_OUTMASK_CH1OM (0x00000002U) /*!< Bit mask for FTM_OUTMASK_CH1OM. */
1879 #define BS_FTM_OUTMASK_CH1OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH1OM. */
1881 /*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
1882 #define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
1884 /*! @brief Format value for bitfield FTM_OUTMASK_CH1OM. */
1885 #define BF_FTM_OUTMASK_CH1OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH1OM) & BM_FTM_OUTMASK_CH1OM)
1887 /*! @brief Set the CH1OM field to a new value. */
1888 #define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
1892 * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
1894 * Defines if the channel output is masked or unmasked.
1897 * - 0 - Channel output is not masked. It continues to operate normally.
1898 * - 1 - Channel output is masked. It is forced to its inactive state.
1901 #define BP_FTM_OUTMASK_CH2OM (2U) /*!< Bit position for FTM_OUTMASK_CH2OM. */
1902 #define BM_FTM_OUTMASK_CH2OM (0x00000004U) /*!< Bit mask for FTM_OUTMASK_CH2OM. */
1903 #define BS_FTM_OUTMASK_CH2OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH2OM. */
1905 /*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
1906 #define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
1908 /*! @brief Format value for bitfield FTM_OUTMASK_CH2OM. */
1909 #define BF_FTM_OUTMASK_CH2OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH2OM) & BM_FTM_OUTMASK_CH2OM)
1911 /*! @brief Set the CH2OM field to a new value. */
1912 #define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
1916 * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
1918 * Defines if the channel output is masked or unmasked.
1921 * - 0 - Channel output is not masked. It continues to operate normally.
1922 * - 1 - Channel output is masked. It is forced to its inactive state.
1925 #define BP_FTM_OUTMASK_CH3OM (3U) /*!< Bit position for FTM_OUTMASK_CH3OM. */
1926 #define BM_FTM_OUTMASK_CH3OM (0x00000008U) /*!< Bit mask for FTM_OUTMASK_CH3OM. */
1927 #define BS_FTM_OUTMASK_CH3OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH3OM. */
1929 /*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
1930 #define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
1932 /*! @brief Format value for bitfield FTM_OUTMASK_CH3OM. */
1933 #define BF_FTM_OUTMASK_CH3OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH3OM) & BM_FTM_OUTMASK_CH3OM)
1935 /*! @brief Set the CH3OM field to a new value. */
1936 #define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
1940 * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
1942 * Defines if the channel output is masked or unmasked.
1945 * - 0 - Channel output is not masked. It continues to operate normally.
1946 * - 1 - Channel output is masked. It is forced to its inactive state.
1949 #define BP_FTM_OUTMASK_CH4OM (4U) /*!< Bit position for FTM_OUTMASK_CH4OM. */
1950 #define BM_FTM_OUTMASK_CH4OM (0x00000010U) /*!< Bit mask for FTM_OUTMASK_CH4OM. */
1951 #define BS_FTM_OUTMASK_CH4OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH4OM. */
1953 /*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
1954 #define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
1956 /*! @brief Format value for bitfield FTM_OUTMASK_CH4OM. */
1957 #define BF_FTM_OUTMASK_CH4OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH4OM) & BM_FTM_OUTMASK_CH4OM)
1959 /*! @brief Set the CH4OM field to a new value. */
1960 #define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
1964 * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
1966 * Defines if the channel output is masked or unmasked.
1969 * - 0 - Channel output is not masked. It continues to operate normally.
1970 * - 1 - Channel output is masked. It is forced to its inactive state.
1973 #define BP_FTM_OUTMASK_CH5OM (5U) /*!< Bit position for FTM_OUTMASK_CH5OM. */
1974 #define BM_FTM_OUTMASK_CH5OM (0x00000020U) /*!< Bit mask for FTM_OUTMASK_CH5OM. */
1975 #define BS_FTM_OUTMASK_CH5OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH5OM. */
1977 /*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
1978 #define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
1980 /*! @brief Format value for bitfield FTM_OUTMASK_CH5OM. */
1981 #define BF_FTM_OUTMASK_CH5OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH5OM) & BM_FTM_OUTMASK_CH5OM)
1983 /*! @brief Set the CH5OM field to a new value. */
1984 #define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
1988 * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
1990 * Defines if the channel output is masked or unmasked.
1993 * - 0 - Channel output is not masked. It continues to operate normally.
1994 * - 1 - Channel output is masked. It is forced to its inactive state.
1997 #define BP_FTM_OUTMASK_CH6OM (6U) /*!< Bit position for FTM_OUTMASK_CH6OM. */
1998 #define BM_FTM_OUTMASK_CH6OM (0x00000040U) /*!< Bit mask for FTM_OUTMASK_CH6OM. */
1999 #define BS_FTM_OUTMASK_CH6OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH6OM. */
2001 /*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
2002 #define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
2004 /*! @brief Format value for bitfield FTM_OUTMASK_CH6OM. */
2005 #define BF_FTM_OUTMASK_CH6OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH6OM) & BM_FTM_OUTMASK_CH6OM)
2007 /*! @brief Set the CH6OM field to a new value. */
2008 #define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
2012 * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
2014 * Defines if the channel output is masked or unmasked.
2017 * - 0 - Channel output is not masked. It continues to operate normally.
2018 * - 1 - Channel output is masked. It is forced to its inactive state.
2021 #define BP_FTM_OUTMASK_CH7OM (7U) /*!< Bit position for FTM_OUTMASK_CH7OM. */
2022 #define BM_FTM_OUTMASK_CH7OM (0x00000080U) /*!< Bit mask for FTM_OUTMASK_CH7OM. */
2023 #define BS_FTM_OUTMASK_CH7OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH7OM. */
2025 /*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
2026 #define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
2028 /*! @brief Format value for bitfield FTM_OUTMASK_CH7OM. */
2029 #define BF_FTM_OUTMASK_CH7OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH7OM) & BM_FTM_OUTMASK_CH7OM)
2031 /*! @brief Set the CH7OM field to a new value. */
2032 #define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
2035 /*******************************************************************************
2036 * HW_FTM_COMBINE - Function For Linked Channels
2037 ******************************************************************************/
2040 * @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
2042 * Reset value: 0x00000000U
2044 * This register contains the control bits used to configure the fault control,
2045 * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
2046 * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
2049 typedef union _hw_ftm_combine
2052 struct _hw_ftm_combine_bitfields
2054 uint32_t COMBINE0 : 1; /*!< [0] Combine Channels For n = 0 */
2055 uint32_t COMP0 : 1; /*!< [1] Complement Of Channel (n) For n = 0 */
2056 uint32_t DECAPEN0 : 1; /*!< [2] Dual Edge Capture Mode Enable For n =
2058 uint32_t DECAP0 : 1; /*!< [3] Dual Edge Capture Mode Captures For n =
2060 uint32_t DTEN0 : 1; /*!< [4] Deadtime Enable For n = 0 */
2061 uint32_t SYNCEN0 : 1; /*!< [5] Synchronization Enable For n = 0 */
2062 uint32_t FAULTEN0 : 1; /*!< [6] Fault Control Enable For n = 0 */
2063 uint32_t RESERVED0 : 1; /*!< [7] */
2064 uint32_t COMBINE1 : 1; /*!< [8] Combine Channels For n = 2 */
2065 uint32_t COMP1 : 1; /*!< [9] Complement Of Channel (n) For n = 2 */
2066 uint32_t DECAPEN1 : 1; /*!< [10] Dual Edge Capture Mode Enable For n
2068 uint32_t DECAP1 : 1; /*!< [11] Dual Edge Capture Mode Captures For n
2070 uint32_t DTEN1 : 1; /*!< [12] Deadtime Enable For n = 2 */
2071 uint32_t SYNCEN1 : 1; /*!< [13] Synchronization Enable For n = 2 */
2072 uint32_t FAULTEN1 : 1; /*!< [14] Fault Control Enable For n = 2 */
2073 uint32_t RESERVED1 : 1; /*!< [15] */
2074 uint32_t COMBINE2 : 1; /*!< [16] Combine Channels For n = 4 */
2075 uint32_t COMP2 : 1; /*!< [17] Complement Of Channel (n) For n = 4 */
2076 uint32_t DECAPEN2 : 1; /*!< [18] Dual Edge Capture Mode Enable For n
2078 uint32_t DECAP2 : 1; /*!< [19] Dual Edge Capture Mode Captures For n
2080 uint32_t DTEN2 : 1; /*!< [20] Deadtime Enable For n = 4 */
2081 uint32_t SYNCEN2 : 1; /*!< [21] Synchronization Enable For n = 4 */
2082 uint32_t FAULTEN2 : 1; /*!< [22] Fault Control Enable For n = 4 */
2083 uint32_t RESERVED2 : 1; /*!< [23] */
2084 uint32_t COMBINE3 : 1; /*!< [24] Combine Channels For n = 6 */
2085 uint32_t COMP3 : 1; /*!< [25] Complement Of Channel (n) for n = 6 */
2086 uint32_t DECAPEN3 : 1; /*!< [26] Dual Edge Capture Mode Enable For n
2088 uint32_t DECAP3 : 1; /*!< [27] Dual Edge Capture Mode Captures For n
2090 uint32_t DTEN3 : 1; /*!< [28] Deadtime Enable For n = 6 */
2091 uint32_t SYNCEN3 : 1; /*!< [29] Synchronization Enable For n = 6 */
2092 uint32_t FAULTEN3 : 1; /*!< [30] Fault Control Enable For n = 6 */
2093 uint32_t RESERVED3 : 1; /*!< [31] */
2098 * @name Constants and macros for entire FTM_COMBINE register
2101 #define HW_FTM_COMBINE_ADDR(x) ((x) + 0x64U)
2103 #define HW_FTM_COMBINE(x) (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x))
2104 #define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U)
2105 #define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v))
2106 #define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) | (v)))
2107 #define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
2108 #define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v)))
2112 * Constants & macros for individual FTM_COMBINE bitfields
2116 * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
2118 * Enables the combine feature for channels (n) and (n+1). This field is write
2119 * protected. It can be written only when MODE[WPDIS] = 1.
2122 * - 0 - Channels (n) and (n+1) are independent.
2123 * - 1 - Channels (n) and (n+1) are combined.
2126 #define BP_FTM_COMBINE_COMBINE0 (0U) /*!< Bit position for FTM_COMBINE_COMBINE0. */
2127 #define BM_FTM_COMBINE_COMBINE0 (0x00000001U) /*!< Bit mask for FTM_COMBINE_COMBINE0. */
2128 #define BS_FTM_COMBINE_COMBINE0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE0. */
2130 /*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
2131 #define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
2133 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE0. */
2134 #define BF_FTM_COMBINE_COMBINE0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE0) & BM_FTM_COMBINE_COMBINE0)
2136 /*! @brief Set the COMBINE0 field to a new value. */
2137 #define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
2141 * @name Register FTM_COMBINE, field COMP0[1] (RW)
2143 * Enables Complementary mode for the combined channels. In Complementary mode
2144 * the channel (n+1) output is the inverse of the channel (n) output. This field
2145 * is write protected. It can be written only when MODE[WPDIS] = 1.
2148 * - 0 - The channel (n+1) output is the same as the channel (n) output.
2149 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
2152 #define BP_FTM_COMBINE_COMP0 (1U) /*!< Bit position for FTM_COMBINE_COMP0. */
2153 #define BM_FTM_COMBINE_COMP0 (0x00000002U) /*!< Bit mask for FTM_COMBINE_COMP0. */
2154 #define BS_FTM_COMBINE_COMP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP0. */
2156 /*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
2157 #define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
2159 /*! @brief Format value for bitfield FTM_COMBINE_COMP0. */
2160 #define BF_FTM_COMBINE_COMP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP0) & BM_FTM_COMBINE_COMP0)
2162 /*! @brief Set the COMP0 field to a new value. */
2163 #define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
2167 * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
2169 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
2170 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
2171 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
2172 * when FTMEN = 1. This field is write protected. It can be written only when
2176 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
2177 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
2180 #define BP_FTM_COMBINE_DECAPEN0 (2U) /*!< Bit position for FTM_COMBINE_DECAPEN0. */
2181 #define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) /*!< Bit mask for FTM_COMBINE_DECAPEN0. */
2182 #define BS_FTM_COMBINE_DECAPEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN0. */
2184 /*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
2185 #define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
2187 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN0. */
2188 #define BF_FTM_COMBINE_DECAPEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN0) & BM_FTM_COMBINE_DECAPEN0)
2190 /*! @brief Set the DECAPEN0 field to a new value. */
2191 #define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
2195 * @name Register FTM_COMBINE, field DECAP0[3] (RW)
2197 * Enables the capture of the FTM counter value according to the channel (n)
2198 * input event and the configuration of the dual edge capture bits. This field
2199 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
2200 * hardware if dual edge capture - one-shot mode is selected and when the capture
2201 * of channel (n+1) event is made.
2204 * - 0 - The dual edge captures are inactive.
2205 * - 1 - The dual edge captures are active.
2208 #define BP_FTM_COMBINE_DECAP0 (3U) /*!< Bit position for FTM_COMBINE_DECAP0. */
2209 #define BM_FTM_COMBINE_DECAP0 (0x00000008U) /*!< Bit mask for FTM_COMBINE_DECAP0. */
2210 #define BS_FTM_COMBINE_DECAP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP0. */
2212 /*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
2213 #define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
2215 /*! @brief Format value for bitfield FTM_COMBINE_DECAP0. */
2216 #define BF_FTM_COMBINE_DECAP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP0) & BM_FTM_COMBINE_DECAP0)
2218 /*! @brief Set the DECAP0 field to a new value. */
2219 #define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
2223 * @name Register FTM_COMBINE, field DTEN0[4] (RW)
2225 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
2226 * write protected. It can be written only when MODE[WPDIS] = 1.
2229 * - 0 - The deadtime insertion in this pair of channels is disabled.
2230 * - 1 - The deadtime insertion in this pair of channels is enabled.
2233 #define BP_FTM_COMBINE_DTEN0 (4U) /*!< Bit position for FTM_COMBINE_DTEN0. */
2234 #define BM_FTM_COMBINE_DTEN0 (0x00000010U) /*!< Bit mask for FTM_COMBINE_DTEN0. */
2235 #define BS_FTM_COMBINE_DTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN0. */
2237 /*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
2238 #define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
2240 /*! @brief Format value for bitfield FTM_COMBINE_DTEN0. */
2241 #define BF_FTM_COMBINE_DTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN0) & BM_FTM_COMBINE_DTEN0)
2243 /*! @brief Set the DTEN0 field to a new value. */
2244 #define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
2248 * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
2250 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
2253 * - 0 - The PWM synchronization in this pair of channels is disabled.
2254 * - 1 - The PWM synchronization in this pair of channels is enabled.
2257 #define BP_FTM_COMBINE_SYNCEN0 (5U) /*!< Bit position for FTM_COMBINE_SYNCEN0. */
2258 #define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) /*!< Bit mask for FTM_COMBINE_SYNCEN0. */
2259 #define BS_FTM_COMBINE_SYNCEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN0. */
2261 /*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
2262 #define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
2264 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN0. */
2265 #define BF_FTM_COMBINE_SYNCEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN0) & BM_FTM_COMBINE_SYNCEN0)
2267 /*! @brief Set the SYNCEN0 field to a new value. */
2268 #define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
2272 * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
2274 * Enables the fault control in channels (n) and (n+1). This field is write
2275 * protected. It can be written only when MODE[WPDIS] = 1.
2278 * - 0 - The fault control in this pair of channels is disabled.
2279 * - 1 - The fault control in this pair of channels is enabled.
2282 #define BP_FTM_COMBINE_FAULTEN0 (6U) /*!< Bit position for FTM_COMBINE_FAULTEN0. */
2283 #define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) /*!< Bit mask for FTM_COMBINE_FAULTEN0. */
2284 #define BS_FTM_COMBINE_FAULTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN0. */
2286 /*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
2287 #define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
2289 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN0. */
2290 #define BF_FTM_COMBINE_FAULTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN0) & BM_FTM_COMBINE_FAULTEN0)
2292 /*! @brief Set the FAULTEN0 field to a new value. */
2293 #define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
2297 * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
2299 * Enables the combine feature for channels (n) and (n+1). This field is write
2300 * protected. It can be written only when MODE[WPDIS] = 1.
2303 * - 0 - Channels (n) and (n+1) are independent.
2304 * - 1 - Channels (n) and (n+1) are combined.
2307 #define BP_FTM_COMBINE_COMBINE1 (8U) /*!< Bit position for FTM_COMBINE_COMBINE1. */
2308 #define BM_FTM_COMBINE_COMBINE1 (0x00000100U) /*!< Bit mask for FTM_COMBINE_COMBINE1. */
2309 #define BS_FTM_COMBINE_COMBINE1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE1. */
2311 /*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
2312 #define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
2314 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE1. */
2315 #define BF_FTM_COMBINE_COMBINE1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE1) & BM_FTM_COMBINE_COMBINE1)
2317 /*! @brief Set the COMBINE1 field to a new value. */
2318 #define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
2322 * @name Register FTM_COMBINE, field COMP1[9] (RW)
2324 * Enables Complementary mode for the combined channels. In Complementary mode
2325 * the channel (n+1) output is the inverse of the channel (n) output. This field
2326 * is write protected. It can be written only when MODE[WPDIS] = 1.
2329 * - 0 - The channel (n+1) output is the same as the channel (n) output.
2330 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
2333 #define BP_FTM_COMBINE_COMP1 (9U) /*!< Bit position for FTM_COMBINE_COMP1. */
2334 #define BM_FTM_COMBINE_COMP1 (0x00000200U) /*!< Bit mask for FTM_COMBINE_COMP1. */
2335 #define BS_FTM_COMBINE_COMP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP1. */
2337 /*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
2338 #define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
2340 /*! @brief Format value for bitfield FTM_COMBINE_COMP1. */
2341 #define BF_FTM_COMBINE_COMP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP1) & BM_FTM_COMBINE_COMP1)
2343 /*! @brief Set the COMP1 field to a new value. */
2344 #define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
2348 * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
2350 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
2351 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
2352 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
2353 * when FTMEN = 1. This field is write protected. It can be written only when
2357 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
2358 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
2361 #define BP_FTM_COMBINE_DECAPEN1 (10U) /*!< Bit position for FTM_COMBINE_DECAPEN1. */
2362 #define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) /*!< Bit mask for FTM_COMBINE_DECAPEN1. */
2363 #define BS_FTM_COMBINE_DECAPEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN1. */
2365 /*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
2366 #define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
2368 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN1. */
2369 #define BF_FTM_COMBINE_DECAPEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN1) & BM_FTM_COMBINE_DECAPEN1)
2371 /*! @brief Set the DECAPEN1 field to a new value. */
2372 #define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
2376 * @name Register FTM_COMBINE, field DECAP1[11] (RW)
2378 * Enables the capture of the FTM counter value according to the channel (n)
2379 * input event and the configuration of the dual edge capture bits. This field
2380 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
2381 * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
2382 * of channel (n+1) event is made.
2385 * - 0 - The dual edge captures are inactive.
2386 * - 1 - The dual edge captures are active.
2389 #define BP_FTM_COMBINE_DECAP1 (11U) /*!< Bit position for FTM_COMBINE_DECAP1. */
2390 #define BM_FTM_COMBINE_DECAP1 (0x00000800U) /*!< Bit mask for FTM_COMBINE_DECAP1. */
2391 #define BS_FTM_COMBINE_DECAP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP1. */
2393 /*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
2394 #define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
2396 /*! @brief Format value for bitfield FTM_COMBINE_DECAP1. */
2397 #define BF_FTM_COMBINE_DECAP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP1) & BM_FTM_COMBINE_DECAP1)
2399 /*! @brief Set the DECAP1 field to a new value. */
2400 #define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
2404 * @name Register FTM_COMBINE, field DTEN1[12] (RW)
2406 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
2407 * write protected. It can be written only when MODE[WPDIS] = 1.
2410 * - 0 - The deadtime insertion in this pair of channels is disabled.
2411 * - 1 - The deadtime insertion in this pair of channels is enabled.
2414 #define BP_FTM_COMBINE_DTEN1 (12U) /*!< Bit position for FTM_COMBINE_DTEN1. */
2415 #define BM_FTM_COMBINE_DTEN1 (0x00001000U) /*!< Bit mask for FTM_COMBINE_DTEN1. */
2416 #define BS_FTM_COMBINE_DTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN1. */
2418 /*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
2419 #define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
2421 /*! @brief Format value for bitfield FTM_COMBINE_DTEN1. */
2422 #define BF_FTM_COMBINE_DTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN1) & BM_FTM_COMBINE_DTEN1)
2424 /*! @brief Set the DTEN1 field to a new value. */
2425 #define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
2429 * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
2431 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
2434 * - 0 - The PWM synchronization in this pair of channels is disabled.
2435 * - 1 - The PWM synchronization in this pair of channels is enabled.
2438 #define BP_FTM_COMBINE_SYNCEN1 (13U) /*!< Bit position for FTM_COMBINE_SYNCEN1. */
2439 #define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) /*!< Bit mask for FTM_COMBINE_SYNCEN1. */
2440 #define BS_FTM_COMBINE_SYNCEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN1. */
2442 /*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
2443 #define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
2445 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN1. */
2446 #define BF_FTM_COMBINE_SYNCEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN1) & BM_FTM_COMBINE_SYNCEN1)
2448 /*! @brief Set the SYNCEN1 field to a new value. */
2449 #define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
2453 * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
2455 * Enables the fault control in channels (n) and (n+1). This field is write
2456 * protected. It can be written only when MODE[WPDIS] = 1.
2459 * - 0 - The fault control in this pair of channels is disabled.
2460 * - 1 - The fault control in this pair of channels is enabled.
2463 #define BP_FTM_COMBINE_FAULTEN1 (14U) /*!< Bit position for FTM_COMBINE_FAULTEN1. */
2464 #define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) /*!< Bit mask for FTM_COMBINE_FAULTEN1. */
2465 #define BS_FTM_COMBINE_FAULTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN1. */
2467 /*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
2468 #define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
2470 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN1. */
2471 #define BF_FTM_COMBINE_FAULTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN1) & BM_FTM_COMBINE_FAULTEN1)
2473 /*! @brief Set the FAULTEN1 field to a new value. */
2474 #define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
2478 * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
2480 * Enables the combine feature for channels (n) and (n+1). This field is write
2481 * protected. It can be written only when MODE[WPDIS] = 1.
2484 * - 0 - Channels (n) and (n+1) are independent.
2485 * - 1 - Channels (n) and (n+1) are combined.
2488 #define BP_FTM_COMBINE_COMBINE2 (16U) /*!< Bit position for FTM_COMBINE_COMBINE2. */
2489 #define BM_FTM_COMBINE_COMBINE2 (0x00010000U) /*!< Bit mask for FTM_COMBINE_COMBINE2. */
2490 #define BS_FTM_COMBINE_COMBINE2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE2. */
2492 /*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
2493 #define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
2495 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE2. */
2496 #define BF_FTM_COMBINE_COMBINE2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE2) & BM_FTM_COMBINE_COMBINE2)
2498 /*! @brief Set the COMBINE2 field to a new value. */
2499 #define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
2503 * @name Register FTM_COMBINE, field COMP2[17] (RW)
2505 * Enables Complementary mode for the combined channels. In Complementary mode
2506 * the channel (n+1) output is the inverse of the channel (n) output. This field
2507 * is write protected. It can be written only when MODE[WPDIS] = 1.
2510 * - 0 - The channel (n+1) output is the same as the channel (n) output.
2511 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
2514 #define BP_FTM_COMBINE_COMP2 (17U) /*!< Bit position for FTM_COMBINE_COMP2. */
2515 #define BM_FTM_COMBINE_COMP2 (0x00020000U) /*!< Bit mask for FTM_COMBINE_COMP2. */
2516 #define BS_FTM_COMBINE_COMP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP2. */
2518 /*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
2519 #define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
2521 /*! @brief Format value for bitfield FTM_COMBINE_COMP2. */
2522 #define BF_FTM_COMBINE_COMP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP2) & BM_FTM_COMBINE_COMP2)
2524 /*! @brief Set the COMP2 field to a new value. */
2525 #define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
2529 * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
2531 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
2532 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
2533 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
2534 * when FTMEN = 1. This field is write protected. It can be written only when
2538 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
2539 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
2542 #define BP_FTM_COMBINE_DECAPEN2 (18U) /*!< Bit position for FTM_COMBINE_DECAPEN2. */
2543 #define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) /*!< Bit mask for FTM_COMBINE_DECAPEN2. */
2544 #define BS_FTM_COMBINE_DECAPEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN2. */
2546 /*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
2547 #define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
2549 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN2. */
2550 #define BF_FTM_COMBINE_DECAPEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN2) & BM_FTM_COMBINE_DECAPEN2)
2552 /*! @brief Set the DECAPEN2 field to a new value. */
2553 #define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
2557 * @name Register FTM_COMBINE, field DECAP2[19] (RW)
2559 * Enables the capture of the FTM counter value according to the channel (n)
2560 * input event and the configuration of the dual edge capture bits. This field
2561 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
2562 * hardware if dual edge capture - one-shot mode is selected and when the capture
2563 * of channel (n+1) event is made.
2566 * - 0 - The dual edge captures are inactive.
2567 * - 1 - The dual edge captures are active.
2570 #define BP_FTM_COMBINE_DECAP2 (19U) /*!< Bit position for FTM_COMBINE_DECAP2. */
2571 #define BM_FTM_COMBINE_DECAP2 (0x00080000U) /*!< Bit mask for FTM_COMBINE_DECAP2. */
2572 #define BS_FTM_COMBINE_DECAP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP2. */
2574 /*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
2575 #define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
2577 /*! @brief Format value for bitfield FTM_COMBINE_DECAP2. */
2578 #define BF_FTM_COMBINE_DECAP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP2) & BM_FTM_COMBINE_DECAP2)
2580 /*! @brief Set the DECAP2 field to a new value. */
2581 #define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
2585 * @name Register FTM_COMBINE, field DTEN2[20] (RW)
2587 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
2588 * write protected. It can be written only when MODE[WPDIS] = 1.
2591 * - 0 - The deadtime insertion in this pair of channels is disabled.
2592 * - 1 - The deadtime insertion in this pair of channels is enabled.
2595 #define BP_FTM_COMBINE_DTEN2 (20U) /*!< Bit position for FTM_COMBINE_DTEN2. */
2596 #define BM_FTM_COMBINE_DTEN2 (0x00100000U) /*!< Bit mask for FTM_COMBINE_DTEN2. */
2597 #define BS_FTM_COMBINE_DTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN2. */
2599 /*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
2600 #define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
2602 /*! @brief Format value for bitfield FTM_COMBINE_DTEN2. */
2603 #define BF_FTM_COMBINE_DTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN2) & BM_FTM_COMBINE_DTEN2)
2605 /*! @brief Set the DTEN2 field to a new value. */
2606 #define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
2610 * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
2612 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
2615 * - 0 - The PWM synchronization in this pair of channels is disabled.
2616 * - 1 - The PWM synchronization in this pair of channels is enabled.
2619 #define BP_FTM_COMBINE_SYNCEN2 (21U) /*!< Bit position for FTM_COMBINE_SYNCEN2. */
2620 #define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) /*!< Bit mask for FTM_COMBINE_SYNCEN2. */
2621 #define BS_FTM_COMBINE_SYNCEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN2. */
2623 /*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
2624 #define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
2626 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN2. */
2627 #define BF_FTM_COMBINE_SYNCEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN2) & BM_FTM_COMBINE_SYNCEN2)
2629 /*! @brief Set the SYNCEN2 field to a new value. */
2630 #define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
2634 * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
2636 * Enables the fault control in channels (n) and (n+1). This field is write
2637 * protected. It can be written only when MODE[WPDIS] = 1.
2640 * - 0 - The fault control in this pair of channels is disabled.
2641 * - 1 - The fault control in this pair of channels is enabled.
2644 #define BP_FTM_COMBINE_FAULTEN2 (22U) /*!< Bit position for FTM_COMBINE_FAULTEN2. */
2645 #define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) /*!< Bit mask for FTM_COMBINE_FAULTEN2. */
2646 #define BS_FTM_COMBINE_FAULTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN2. */
2648 /*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
2649 #define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
2651 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN2. */
2652 #define BF_FTM_COMBINE_FAULTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN2) & BM_FTM_COMBINE_FAULTEN2)
2654 /*! @brief Set the FAULTEN2 field to a new value. */
2655 #define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
2659 * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
2661 * Enables the combine feature for channels (n) and (n+1). This field is write
2662 * protected. It can be written only when MODE[WPDIS] = 1.
2665 * - 0 - Channels (n) and (n+1) are independent.
2666 * - 1 - Channels (n) and (n+1) are combined.
2669 #define BP_FTM_COMBINE_COMBINE3 (24U) /*!< Bit position for FTM_COMBINE_COMBINE3. */
2670 #define BM_FTM_COMBINE_COMBINE3 (0x01000000U) /*!< Bit mask for FTM_COMBINE_COMBINE3. */
2671 #define BS_FTM_COMBINE_COMBINE3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE3. */
2673 /*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
2674 #define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
2676 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE3. */
2677 #define BF_FTM_COMBINE_COMBINE3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE3) & BM_FTM_COMBINE_COMBINE3)
2679 /*! @brief Set the COMBINE3 field to a new value. */
2680 #define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
2684 * @name Register FTM_COMBINE, field COMP3[25] (RW)
2686 * Enables Complementary mode for the combined channels. In Complementary mode
2687 * the channel (n+1) output is the inverse of the channel (n) output. This field
2688 * is write protected. It can be written only when MODE[WPDIS] = 1.
2691 * - 0 - The channel (n+1) output is the same as the channel (n) output.
2692 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
2695 #define BP_FTM_COMBINE_COMP3 (25U) /*!< Bit position for FTM_COMBINE_COMP3. */
2696 #define BM_FTM_COMBINE_COMP3 (0x02000000U) /*!< Bit mask for FTM_COMBINE_COMP3. */
2697 #define BS_FTM_COMBINE_COMP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP3. */
2699 /*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
2700 #define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
2702 /*! @brief Format value for bitfield FTM_COMBINE_COMP3. */
2703 #define BF_FTM_COMBINE_COMP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP3) & BM_FTM_COMBINE_COMP3)
2705 /*! @brief Set the COMP3 field to a new value. */
2706 #define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
2710 * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
2712 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
2713 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
2714 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
2715 * when FTMEN = 1. This field is write protected. It can be written only when
2719 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
2720 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
2723 #define BP_FTM_COMBINE_DECAPEN3 (26U) /*!< Bit position for FTM_COMBINE_DECAPEN3. */
2724 #define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) /*!< Bit mask for FTM_COMBINE_DECAPEN3. */
2725 #define BS_FTM_COMBINE_DECAPEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN3. */
2727 /*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
2728 #define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
2730 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN3. */
2731 #define BF_FTM_COMBINE_DECAPEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN3) & BM_FTM_COMBINE_DECAPEN3)
2733 /*! @brief Set the DECAPEN3 field to a new value. */
2734 #define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
2738 * @name Register FTM_COMBINE, field DECAP3[27] (RW)
2740 * Enables the capture of the FTM counter value according to the channel (n)
2741 * input event and the configuration of the dual edge capture bits. This field
2742 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
2743 * hardware if dual edge capture - one-shot mode is selected and when the capture
2744 * of channel (n+1) event is made.
2747 * - 0 - The dual edge captures are inactive.
2748 * - 1 - The dual edge captures are active.
2751 #define BP_FTM_COMBINE_DECAP3 (27U) /*!< Bit position for FTM_COMBINE_DECAP3. */
2752 #define BM_FTM_COMBINE_DECAP3 (0x08000000U) /*!< Bit mask for FTM_COMBINE_DECAP3. */
2753 #define BS_FTM_COMBINE_DECAP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP3. */
2755 /*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
2756 #define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
2758 /*! @brief Format value for bitfield FTM_COMBINE_DECAP3. */
2759 #define BF_FTM_COMBINE_DECAP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP3) & BM_FTM_COMBINE_DECAP3)
2761 /*! @brief Set the DECAP3 field to a new value. */
2762 #define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
2766 * @name Register FTM_COMBINE, field DTEN3[28] (RW)
2768 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
2769 * write protected. It can be written only when MODE[WPDIS] = 1.
2772 * - 0 - The deadtime insertion in this pair of channels is disabled.
2773 * - 1 - The deadtime insertion in this pair of channels is enabled.
2776 #define BP_FTM_COMBINE_DTEN3 (28U) /*!< Bit position for FTM_COMBINE_DTEN3. */
2777 #define BM_FTM_COMBINE_DTEN3 (0x10000000U) /*!< Bit mask for FTM_COMBINE_DTEN3. */
2778 #define BS_FTM_COMBINE_DTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN3. */
2780 /*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
2781 #define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
2783 /*! @brief Format value for bitfield FTM_COMBINE_DTEN3. */
2784 #define BF_FTM_COMBINE_DTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN3) & BM_FTM_COMBINE_DTEN3)
2786 /*! @brief Set the DTEN3 field to a new value. */
2787 #define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
2791 * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
2793 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
2796 * - 0 - The PWM synchronization in this pair of channels is disabled.
2797 * - 1 - The PWM synchronization in this pair of channels is enabled.
2800 #define BP_FTM_COMBINE_SYNCEN3 (29U) /*!< Bit position for FTM_COMBINE_SYNCEN3. */
2801 #define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) /*!< Bit mask for FTM_COMBINE_SYNCEN3. */
2802 #define BS_FTM_COMBINE_SYNCEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN3. */
2804 /*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
2805 #define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
2807 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN3. */
2808 #define BF_FTM_COMBINE_SYNCEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN3) & BM_FTM_COMBINE_SYNCEN3)
2810 /*! @brief Set the SYNCEN3 field to a new value. */
2811 #define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
2815 * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
2817 * Enables the fault control in channels (n) and (n+1). This field is write
2818 * protected. It can be written only when MODE[WPDIS] = 1.
2821 * - 0 - The fault control in this pair of channels is disabled.
2822 * - 1 - The fault control in this pair of channels is enabled.
2825 #define BP_FTM_COMBINE_FAULTEN3 (30U) /*!< Bit position for FTM_COMBINE_FAULTEN3. */
2826 #define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) /*!< Bit mask for FTM_COMBINE_FAULTEN3. */
2827 #define BS_FTM_COMBINE_FAULTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN3. */
2829 /*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
2830 #define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
2832 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN3. */
2833 #define BF_FTM_COMBINE_FAULTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN3) & BM_FTM_COMBINE_FAULTEN3)
2835 /*! @brief Set the FAULTEN3 field to a new value. */
2836 #define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
2839 /*******************************************************************************
2840 * HW_FTM_DEADTIME - Deadtime Insertion Control
2841 ******************************************************************************/
2844 * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
2846 * Reset value: 0x00000000U
2848 * This register selects the deadtime prescaler factor and deadtime value. All
2849 * FTM channels use this clock prescaler and this deadtime value for the deadtime
2852 typedef union _hw_ftm_deadtime
2855 struct _hw_ftm_deadtime_bitfields
2857 uint32_t DTVAL : 6; /*!< [5:0] Deadtime Value */
2858 uint32_t DTPS : 2; /*!< [7:6] Deadtime Prescaler Value */
2859 uint32_t RESERVED0 : 24; /*!< [31:8] */
2861 } hw_ftm_deadtime_t;
2864 * @name Constants and macros for entire FTM_DEADTIME register
2867 #define HW_FTM_DEADTIME_ADDR(x) ((x) + 0x68U)
2869 #define HW_FTM_DEADTIME(x) (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x))
2870 #define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U)
2871 #define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
2872 #define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) | (v)))
2873 #define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
2874 #define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v)))
2878 * Constants & macros for individual FTM_DEADTIME bitfields
2882 * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
2884 * Selects the deadtime insertion value for the deadtime counter. The deadtime
2885 * counter is clocked by a scaled version of the system clock. See the description
2886 * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
2887 * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
2888 * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
2889 * This pattern continues up to a possible 63 counts. This field is write
2890 * protected. It can be written only when MODE[WPDIS] = 1.
2893 #define BP_FTM_DEADTIME_DTVAL (0U) /*!< Bit position for FTM_DEADTIME_DTVAL. */
2894 #define BM_FTM_DEADTIME_DTVAL (0x0000003FU) /*!< Bit mask for FTM_DEADTIME_DTVAL. */
2895 #define BS_FTM_DEADTIME_DTVAL (6U) /*!< Bit field size in bits for FTM_DEADTIME_DTVAL. */
2897 /*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
2898 #define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
2900 /*! @brief Format value for bitfield FTM_DEADTIME_DTVAL. */
2901 #define BF_FTM_DEADTIME_DTVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTVAL) & BM_FTM_DEADTIME_DTVAL)
2903 /*! @brief Set the DTVAL field to a new value. */
2904 #define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v)))
2908 * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
2910 * Selects the division factor of the system clock. This prescaled clock is used
2911 * by the deadtime counter. This field is write protected. It can be written
2912 * only when MODE[WPDIS] = 1.
2915 * - 0x - Divide the system clock by 1.
2916 * - 10 - Divide the system clock by 4.
2917 * - 11 - Divide the system clock by 16.
2920 #define BP_FTM_DEADTIME_DTPS (6U) /*!< Bit position for FTM_DEADTIME_DTPS. */
2921 #define BM_FTM_DEADTIME_DTPS (0x000000C0U) /*!< Bit mask for FTM_DEADTIME_DTPS. */
2922 #define BS_FTM_DEADTIME_DTPS (2U) /*!< Bit field size in bits for FTM_DEADTIME_DTPS. */
2924 /*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
2925 #define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
2927 /*! @brief Format value for bitfield FTM_DEADTIME_DTPS. */
2928 #define BF_FTM_DEADTIME_DTPS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTPS) & BM_FTM_DEADTIME_DTPS)
2930 /*! @brief Set the DTPS field to a new value. */
2931 #define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v)))
2934 /*******************************************************************************
2935 * HW_FTM_EXTTRIG - FTM External Trigger
2936 ******************************************************************************/
2939 * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
2941 * Reset value: 0x00000000U
2943 * This register: Indicates when a channel trigger was generated Enables the
2944 * generation of a trigger when the FTM counter is equal to its initial value
2945 * Selects which channels are used in the generation of the channel triggers Several
2946 * channels can be selected to generate multiple triggers in one PWM period.
2947 * Channels 6 and 7 are not used to generate channel triggers.
2949 typedef union _hw_ftm_exttrig
2952 struct _hw_ftm_exttrig_bitfields
2954 uint32_t CH2TRIG : 1; /*!< [0] Channel 2 Trigger Enable */
2955 uint32_t CH3TRIG : 1; /*!< [1] Channel 3 Trigger Enable */
2956 uint32_t CH4TRIG : 1; /*!< [2] Channel 4 Trigger Enable */
2957 uint32_t CH5TRIG : 1; /*!< [3] Channel 5 Trigger Enable */
2958 uint32_t CH0TRIG : 1; /*!< [4] Channel 0 Trigger Enable */
2959 uint32_t CH1TRIG : 1; /*!< [5] Channel 1 Trigger Enable */
2960 uint32_t INITTRIGEN : 1; /*!< [6] Initialization Trigger Enable */
2961 uint32_t TRIGF : 1; /*!< [7] Channel Trigger Flag */
2962 uint32_t RESERVED0 : 24; /*!< [31:8] */
2967 * @name Constants and macros for entire FTM_EXTTRIG register
2970 #define HW_FTM_EXTTRIG_ADDR(x) ((x) + 0x6CU)
2972 #define HW_FTM_EXTTRIG(x) (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x))
2973 #define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U)
2974 #define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v))
2975 #define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) | (v)))
2976 #define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
2977 #define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v)))
2981 * Constants & macros for individual FTM_EXTTRIG bitfields
2985 * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
2987 * Enables the generation of the channel trigger when the FTM counter is equal
2988 * to the CnV register.
2991 * - 0 - The generation of the channel trigger is disabled.
2992 * - 1 - The generation of the channel trigger is enabled.
2995 #define BP_FTM_EXTTRIG_CH2TRIG (0U) /*!< Bit position for FTM_EXTTRIG_CH2TRIG. */
2996 #define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) /*!< Bit mask for FTM_EXTTRIG_CH2TRIG. */
2997 #define BS_FTM_EXTTRIG_CH2TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG. */
2999 /*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
3000 #define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
3002 /*! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG. */
3003 #define BF_FTM_EXTTRIG_CH2TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH2TRIG) & BM_FTM_EXTTRIG_CH2TRIG)
3005 /*! @brief Set the CH2TRIG field to a new value. */
3006 #define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
3010 * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
3012 * Enables the generation of the channel trigger when the FTM counter is equal
3013 * to the CnV register.
3016 * - 0 - The generation of the channel trigger is disabled.
3017 * - 1 - The generation of the channel trigger is enabled.
3020 #define BP_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit position for FTM_EXTTRIG_CH3TRIG. */
3021 #define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) /*!< Bit mask for FTM_EXTTRIG_CH3TRIG. */
3022 #define BS_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG. */
3024 /*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
3025 #define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
3027 /*! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG. */
3028 #define BF_FTM_EXTTRIG_CH3TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH3TRIG) & BM_FTM_EXTTRIG_CH3TRIG)
3030 /*! @brief Set the CH3TRIG field to a new value. */
3031 #define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
3035 * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
3037 * Enables the generation of the channel trigger when the FTM counter is equal
3038 * to the CnV register.
3041 * - 0 - The generation of the channel trigger is disabled.
3042 * - 1 - The generation of the channel trigger is enabled.
3045 #define BP_FTM_EXTTRIG_CH4TRIG (2U) /*!< Bit position for FTM_EXTTRIG_CH4TRIG. */
3046 #define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) /*!< Bit mask for FTM_EXTTRIG_CH4TRIG. */
3047 #define BS_FTM_EXTTRIG_CH4TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG. */
3049 /*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
3050 #define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
3052 /*! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG. */
3053 #define BF_FTM_EXTTRIG_CH4TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH4TRIG) & BM_FTM_EXTTRIG_CH4TRIG)
3055 /*! @brief Set the CH4TRIG field to a new value. */
3056 #define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
3060 * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
3062 * Enables the generation of the channel trigger when the FTM counter is equal
3063 * to the CnV register.
3066 * - 0 - The generation of the channel trigger is disabled.
3067 * - 1 - The generation of the channel trigger is enabled.
3070 #define BP_FTM_EXTTRIG_CH5TRIG (3U) /*!< Bit position for FTM_EXTTRIG_CH5TRIG. */
3071 #define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) /*!< Bit mask for FTM_EXTTRIG_CH5TRIG. */
3072 #define BS_FTM_EXTTRIG_CH5TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG. */
3074 /*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
3075 #define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
3077 /*! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG. */
3078 #define BF_FTM_EXTTRIG_CH5TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH5TRIG) & BM_FTM_EXTTRIG_CH5TRIG)
3080 /*! @brief Set the CH5TRIG field to a new value. */
3081 #define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
3085 * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
3087 * Enables the generation of the channel trigger when the FTM counter is equal
3088 * to the CnV register.
3091 * - 0 - The generation of the channel trigger is disabled.
3092 * - 1 - The generation of the channel trigger is enabled.
3095 #define BP_FTM_EXTTRIG_CH0TRIG (4U) /*!< Bit position for FTM_EXTTRIG_CH0TRIG. */
3096 #define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) /*!< Bit mask for FTM_EXTTRIG_CH0TRIG. */
3097 #define BS_FTM_EXTTRIG_CH0TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG. */
3099 /*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
3100 #define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
3102 /*! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG. */
3103 #define BF_FTM_EXTTRIG_CH0TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH0TRIG) & BM_FTM_EXTTRIG_CH0TRIG)
3105 /*! @brief Set the CH0TRIG field to a new value. */
3106 #define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
3110 * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
3112 * Enables the generation of the channel trigger when the FTM counter is equal
3113 * to the CnV register.
3116 * - 0 - The generation of the channel trigger is disabled.
3117 * - 1 - The generation of the channel trigger is enabled.
3120 #define BP_FTM_EXTTRIG_CH1TRIG (5U) /*!< Bit position for FTM_EXTTRIG_CH1TRIG. */
3121 #define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) /*!< Bit mask for FTM_EXTTRIG_CH1TRIG. */
3122 #define BS_FTM_EXTTRIG_CH1TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG. */
3124 /*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
3125 #define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
3127 /*! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG. */
3128 #define BF_FTM_EXTTRIG_CH1TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH1TRIG) & BM_FTM_EXTTRIG_CH1TRIG)
3130 /*! @brief Set the CH1TRIG field to a new value. */
3131 #define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
3135 * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
3137 * Enables the generation of the trigger when the FTM counter is equal to the
3141 * - 0 - The generation of initialization trigger is disabled.
3142 * - 1 - The generation of initialization trigger is enabled.
3145 #define BP_FTM_EXTTRIG_INITTRIGEN (6U) /*!< Bit position for FTM_EXTTRIG_INITTRIGEN. */
3146 #define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) /*!< Bit mask for FTM_EXTTRIG_INITTRIGEN. */
3147 #define BS_FTM_EXTTRIG_INITTRIGEN (1U) /*!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN. */
3149 /*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
3150 #define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
3152 /*! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN. */
3153 #define BF_FTM_EXTTRIG_INITTRIGEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_INITTRIGEN) & BM_FTM_EXTTRIG_INITTRIGEN)
3155 /*! @brief Set the INITTRIGEN field to a new value. */
3156 #define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
3160 * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
3162 * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
3163 * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
3164 * has no effect. If another channel trigger is generated before the clearing
3165 * sequence is completed, the sequence is reset so TRIGF remains set after the clear
3166 * sequence is completed for the earlier TRIGF.
3169 * - 0 - No channel trigger was generated.
3170 * - 1 - A channel trigger was generated.
3173 #define BP_FTM_EXTTRIG_TRIGF (7U) /*!< Bit position for FTM_EXTTRIG_TRIGF. */
3174 #define BM_FTM_EXTTRIG_TRIGF (0x00000080U) /*!< Bit mask for FTM_EXTTRIG_TRIGF. */
3175 #define BS_FTM_EXTTRIG_TRIGF (1U) /*!< Bit field size in bits for FTM_EXTTRIG_TRIGF. */
3177 /*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
3178 #define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
3180 /*! @brief Format value for bitfield FTM_EXTTRIG_TRIGF. */
3181 #define BF_FTM_EXTTRIG_TRIGF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_TRIGF) & BM_FTM_EXTTRIG_TRIGF)
3183 /*! @brief Set the TRIGF field to a new value. */
3184 #define BW_FTM_EXTTRIG_TRIGF(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF) = (v))
3187 /*******************************************************************************
3188 * HW_FTM_POL - Channels Polarity
3189 ******************************************************************************/
3192 * @brief HW_FTM_POL - Channels Polarity (RW)
3194 * Reset value: 0x00000000U
3196 * This register defines the output polarity of the FTM channels. The safe value
3197 * that is driven in a channel output when the fault control is enabled and a
3198 * fault condition is detected is the inactive state of the channel. That is, the
3199 * safe value of a channel is the value of its POL bit.
3201 typedef union _hw_ftm_pol
3204 struct _hw_ftm_pol_bitfields
3206 uint32_t POL0 : 1; /*!< [0] Channel 0 Polarity */
3207 uint32_t POL1 : 1; /*!< [1] Channel 1 Polarity */
3208 uint32_t POL2 : 1; /*!< [2] Channel 2 Polarity */
3209 uint32_t POL3 : 1; /*!< [3] Channel 3 Polarity */
3210 uint32_t POL4 : 1; /*!< [4] Channel 4 Polarity */
3211 uint32_t POL5 : 1; /*!< [5] Channel 5 Polarity */
3212 uint32_t POL6 : 1; /*!< [6] Channel 6 Polarity */
3213 uint32_t POL7 : 1; /*!< [7] Channel 7 Polarity */
3214 uint32_t RESERVED0 : 24; /*!< [31:8] */
3219 * @name Constants and macros for entire FTM_POL register
3222 #define HW_FTM_POL_ADDR(x) ((x) + 0x70U)
3224 #define HW_FTM_POL(x) (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x))
3225 #define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U)
3226 #define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v))
3227 #define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) | (v)))
3228 #define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
3229 #define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v)))
3233 * Constants & macros for individual FTM_POL bitfields
3237 * @name Register FTM_POL, field POL0[0] (RW)
3239 * Defines the polarity of the channel output. This field is write protected. It
3240 * can be written only when MODE[WPDIS] = 1.
3243 * - 0 - The channel polarity is active high.
3244 * - 1 - The channel polarity is active low.
3247 #define BP_FTM_POL_POL0 (0U) /*!< Bit position for FTM_POL_POL0. */
3248 #define BM_FTM_POL_POL0 (0x00000001U) /*!< Bit mask for FTM_POL_POL0. */
3249 #define BS_FTM_POL_POL0 (1U) /*!< Bit field size in bits for FTM_POL_POL0. */
3251 /*! @brief Read current value of the FTM_POL_POL0 field. */
3252 #define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
3254 /*! @brief Format value for bitfield FTM_POL_POL0. */
3255 #define BF_FTM_POL_POL0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL0) & BM_FTM_POL_POL0)
3257 /*! @brief Set the POL0 field to a new value. */
3258 #define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
3262 * @name Register FTM_POL, field POL1[1] (RW)
3264 * Defines the polarity of the channel output. This field is write protected. It
3265 * can be written only when MODE[WPDIS] = 1.
3268 * - 0 - The channel polarity is active high.
3269 * - 1 - The channel polarity is active low.
3272 #define BP_FTM_POL_POL1 (1U) /*!< Bit position for FTM_POL_POL1. */
3273 #define BM_FTM_POL_POL1 (0x00000002U) /*!< Bit mask for FTM_POL_POL1. */
3274 #define BS_FTM_POL_POL1 (1U) /*!< Bit field size in bits for FTM_POL_POL1. */
3276 /*! @brief Read current value of the FTM_POL_POL1 field. */
3277 #define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
3279 /*! @brief Format value for bitfield FTM_POL_POL1. */
3280 #define BF_FTM_POL_POL1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL1) & BM_FTM_POL_POL1)
3282 /*! @brief Set the POL1 field to a new value. */
3283 #define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
3287 * @name Register FTM_POL, field POL2[2] (RW)
3289 * Defines the polarity of the channel output. This field is write protected. It
3290 * can be written only when MODE[WPDIS] = 1.
3293 * - 0 - The channel polarity is active high.
3294 * - 1 - The channel polarity is active low.
3297 #define BP_FTM_POL_POL2 (2U) /*!< Bit position for FTM_POL_POL2. */
3298 #define BM_FTM_POL_POL2 (0x00000004U) /*!< Bit mask for FTM_POL_POL2. */
3299 #define BS_FTM_POL_POL2 (1U) /*!< Bit field size in bits for FTM_POL_POL2. */
3301 /*! @brief Read current value of the FTM_POL_POL2 field. */
3302 #define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
3304 /*! @brief Format value for bitfield FTM_POL_POL2. */
3305 #define BF_FTM_POL_POL2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL2) & BM_FTM_POL_POL2)
3307 /*! @brief Set the POL2 field to a new value. */
3308 #define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
3312 * @name Register FTM_POL, field POL3[3] (RW)
3314 * Defines the polarity of the channel output. This field is write protected. It
3315 * can be written only when MODE[WPDIS] = 1.
3318 * - 0 - The channel polarity is active high.
3319 * - 1 - The channel polarity is active low.
3322 #define BP_FTM_POL_POL3 (3U) /*!< Bit position for FTM_POL_POL3. */
3323 #define BM_FTM_POL_POL3 (0x00000008U) /*!< Bit mask for FTM_POL_POL3. */
3324 #define BS_FTM_POL_POL3 (1U) /*!< Bit field size in bits for FTM_POL_POL3. */
3326 /*! @brief Read current value of the FTM_POL_POL3 field. */
3327 #define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
3329 /*! @brief Format value for bitfield FTM_POL_POL3. */
3330 #define BF_FTM_POL_POL3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL3) & BM_FTM_POL_POL3)
3332 /*! @brief Set the POL3 field to a new value. */
3333 #define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
3337 * @name Register FTM_POL, field POL4[4] (RW)
3339 * Defines the polarity of the channel output. This field is write protected. It
3340 * can be written only when MODE[WPDIS] = 1.
3343 * - 0 - The channel polarity is active high.
3344 * - 1 - The channel polarity is active low.
3347 #define BP_FTM_POL_POL4 (4U) /*!< Bit position for FTM_POL_POL4. */
3348 #define BM_FTM_POL_POL4 (0x00000010U) /*!< Bit mask for FTM_POL_POL4. */
3349 #define BS_FTM_POL_POL4 (1U) /*!< Bit field size in bits for FTM_POL_POL4. */
3351 /*! @brief Read current value of the FTM_POL_POL4 field. */
3352 #define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
3354 /*! @brief Format value for bitfield FTM_POL_POL4. */
3355 #define BF_FTM_POL_POL4(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL4) & BM_FTM_POL_POL4)
3357 /*! @brief Set the POL4 field to a new value. */
3358 #define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
3362 * @name Register FTM_POL, field POL5[5] (RW)
3364 * Defines the polarity of the channel output. This field is write protected. It
3365 * can be written only when MODE[WPDIS] = 1.
3368 * - 0 - The channel polarity is active high.
3369 * - 1 - The channel polarity is active low.
3372 #define BP_FTM_POL_POL5 (5U) /*!< Bit position for FTM_POL_POL5. */
3373 #define BM_FTM_POL_POL5 (0x00000020U) /*!< Bit mask for FTM_POL_POL5. */
3374 #define BS_FTM_POL_POL5 (1U) /*!< Bit field size in bits for FTM_POL_POL5. */
3376 /*! @brief Read current value of the FTM_POL_POL5 field. */
3377 #define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
3379 /*! @brief Format value for bitfield FTM_POL_POL5. */
3380 #define BF_FTM_POL_POL5(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL5) & BM_FTM_POL_POL5)
3382 /*! @brief Set the POL5 field to a new value. */
3383 #define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
3387 * @name Register FTM_POL, field POL6[6] (RW)
3389 * Defines the polarity of the channel output. This field is write protected. It
3390 * can be written only when MODE[WPDIS] = 1.
3393 * - 0 - The channel polarity is active high.
3394 * - 1 - The channel polarity is active low.
3397 #define BP_FTM_POL_POL6 (6U) /*!< Bit position for FTM_POL_POL6. */
3398 #define BM_FTM_POL_POL6 (0x00000040U) /*!< Bit mask for FTM_POL_POL6. */
3399 #define BS_FTM_POL_POL6 (1U) /*!< Bit field size in bits for FTM_POL_POL6. */
3401 /*! @brief Read current value of the FTM_POL_POL6 field. */
3402 #define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
3404 /*! @brief Format value for bitfield FTM_POL_POL6. */
3405 #define BF_FTM_POL_POL6(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL6) & BM_FTM_POL_POL6)
3407 /*! @brief Set the POL6 field to a new value. */
3408 #define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
3412 * @name Register FTM_POL, field POL7[7] (RW)
3414 * Defines the polarity of the channel output. This field is write protected. It
3415 * can be written only when MODE[WPDIS] = 1.
3418 * - 0 - The channel polarity is active high.
3419 * - 1 - The channel polarity is active low.
3422 #define BP_FTM_POL_POL7 (7U) /*!< Bit position for FTM_POL_POL7. */
3423 #define BM_FTM_POL_POL7 (0x00000080U) /*!< Bit mask for FTM_POL_POL7. */
3424 #define BS_FTM_POL_POL7 (1U) /*!< Bit field size in bits for FTM_POL_POL7. */
3426 /*! @brief Read current value of the FTM_POL_POL7 field. */
3427 #define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
3429 /*! @brief Format value for bitfield FTM_POL_POL7. */
3430 #define BF_FTM_POL_POL7(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL7) & BM_FTM_POL_POL7)
3432 /*! @brief Set the POL7 field to a new value. */
3433 #define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
3436 /*******************************************************************************
3437 * HW_FTM_FMS - Fault Mode Status
3438 ******************************************************************************/
3441 * @brief HW_FTM_FMS - Fault Mode Status (RW)
3443 * Reset value: 0x00000000U
3445 * This register contains the fault detection flags, write protection enable
3446 * bit, and the logic OR of the enabled fault inputs.
3448 typedef union _hw_ftm_fms
3451 struct _hw_ftm_fms_bitfields
3453 uint32_t FAULTF0 : 1; /*!< [0] Fault Detection Flag 0 */
3454 uint32_t FAULTF1 : 1; /*!< [1] Fault Detection Flag 1 */
3455 uint32_t FAULTF2 : 1; /*!< [2] Fault Detection Flag 2 */
3456 uint32_t FAULTF3 : 1; /*!< [3] Fault Detection Flag 3 */
3457 uint32_t RESERVED0 : 1; /*!< [4] */
3458 uint32_t FAULTIN : 1; /*!< [5] Fault Inputs */
3459 uint32_t WPEN : 1; /*!< [6] Write Protection Enable */
3460 uint32_t FAULTF : 1; /*!< [7] Fault Detection Flag */
3461 uint32_t RESERVED1 : 24; /*!< [31:8] */
3466 * @name Constants and macros for entire FTM_FMS register
3469 #define HW_FTM_FMS_ADDR(x) ((x) + 0x74U)
3471 #define HW_FTM_FMS(x) (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x))
3472 #define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U)
3473 #define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v))
3474 #define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) | (v)))
3475 #define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
3476 #define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v)))
3480 * Constants & macros for individual FTM_FMS bitfields
3484 * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
3486 * Set by hardware when fault control is enabled, the corresponding fault input
3487 * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
3488 * by reading the FMS register while FAULTF0 is set and then writing a 0 to
3489 * FAULTF0 while there is no existing fault condition at the corresponding fault
3490 * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
3491 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
3492 * fault input before the clearing sequence is completed, the sequence is reset
3493 * so FAULTF0 remains set after the clearing sequence is completed for the
3494 * earlier fault condition.
3497 * - 0 - No fault condition was detected at the fault input.
3498 * - 1 - A fault condition was detected at the fault input.
3501 #define BP_FTM_FMS_FAULTF0 (0U) /*!< Bit position for FTM_FMS_FAULTF0. */
3502 #define BM_FTM_FMS_FAULTF0 (0x00000001U) /*!< Bit mask for FTM_FMS_FAULTF0. */
3503 #define BS_FTM_FMS_FAULTF0 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF0. */
3505 /*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
3506 #define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
3508 /*! @brief Format value for bitfield FTM_FMS_FAULTF0. */
3509 #define BF_FTM_FMS_FAULTF0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF0) & BM_FTM_FMS_FAULTF0)
3511 /*! @brief Set the FAULTF0 field to a new value. */
3512 #define BW_FTM_FMS_FAULTF0(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0) = (v))
3516 * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
3518 * Set by hardware when fault control is enabled, the corresponding fault input
3519 * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
3520 * by reading the FMS register while FAULTF1 is set and then writing a 0 to
3521 * FAULTF1 while there is no existing fault condition at the corresponding fault
3522 * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
3523 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
3524 * fault input before the clearing sequence is completed, the sequence is reset
3525 * so FAULTF1 remains set after the clearing sequence is completed for the
3526 * earlier fault condition.
3529 * - 0 - No fault condition was detected at the fault input.
3530 * - 1 - A fault condition was detected at the fault input.
3533 #define BP_FTM_FMS_FAULTF1 (1U) /*!< Bit position for FTM_FMS_FAULTF1. */
3534 #define BM_FTM_FMS_FAULTF1 (0x00000002U) /*!< Bit mask for FTM_FMS_FAULTF1. */
3535 #define BS_FTM_FMS_FAULTF1 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF1. */
3537 /*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
3538 #define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
3540 /*! @brief Format value for bitfield FTM_FMS_FAULTF1. */
3541 #define BF_FTM_FMS_FAULTF1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF1) & BM_FTM_FMS_FAULTF1)
3543 /*! @brief Set the FAULTF1 field to a new value. */
3544 #define BW_FTM_FMS_FAULTF1(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1) = (v))
3548 * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
3550 * Set by hardware when fault control is enabled, the corresponding fault input
3551 * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
3552 * by reading the FMS register while FAULTF2 is set and then writing a 0 to
3553 * FAULTF2 while there is no existing fault condition at the corresponding fault
3554 * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
3555 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
3556 * fault input before the clearing sequence is completed, the sequence is reset
3557 * so FAULTF2 remains set after the clearing sequence is completed for the
3558 * earlier fault condition.
3561 * - 0 - No fault condition was detected at the fault input.
3562 * - 1 - A fault condition was detected at the fault input.
3565 #define BP_FTM_FMS_FAULTF2 (2U) /*!< Bit position for FTM_FMS_FAULTF2. */
3566 #define BM_FTM_FMS_FAULTF2 (0x00000004U) /*!< Bit mask for FTM_FMS_FAULTF2. */
3567 #define BS_FTM_FMS_FAULTF2 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF2. */
3569 /*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
3570 #define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
3572 /*! @brief Format value for bitfield FTM_FMS_FAULTF2. */
3573 #define BF_FTM_FMS_FAULTF2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF2) & BM_FTM_FMS_FAULTF2)
3575 /*! @brief Set the FAULTF2 field to a new value. */
3576 #define BW_FTM_FMS_FAULTF2(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2) = (v))
3580 * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
3582 * Set by hardware when fault control is enabled, the corresponding fault input
3583 * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
3584 * by reading the FMS register while FAULTF3 is set and then writing a 0 to
3585 * FAULTF3 while there is no existing fault condition at the corresponding fault
3586 * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
3587 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
3588 * fault input before the clearing sequence is completed, the sequence is reset
3589 * so FAULTF3 remains set after the clearing sequence is completed for the
3590 * earlier fault condition.
3593 * - 0 - No fault condition was detected at the fault input.
3594 * - 1 - A fault condition was detected at the fault input.
3597 #define BP_FTM_FMS_FAULTF3 (3U) /*!< Bit position for FTM_FMS_FAULTF3. */
3598 #define BM_FTM_FMS_FAULTF3 (0x00000008U) /*!< Bit mask for FTM_FMS_FAULTF3. */
3599 #define BS_FTM_FMS_FAULTF3 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF3. */
3601 /*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
3602 #define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
3604 /*! @brief Format value for bitfield FTM_FMS_FAULTF3. */
3605 #define BF_FTM_FMS_FAULTF3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF3) & BM_FTM_FMS_FAULTF3)
3607 /*! @brief Set the FAULTF3 field to a new value. */
3608 #define BW_FTM_FMS_FAULTF3(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3) = (v))
3612 * @name Register FTM_FMS, field FAULTIN[5] (RO)
3614 * Represents the logic OR of the enabled fault inputs after their filter (if
3615 * their filter is enabled) when fault control is enabled.
3618 * - 0 - The logic OR of the enabled fault inputs is 0.
3619 * - 1 - The logic OR of the enabled fault inputs is 1.
3622 #define BP_FTM_FMS_FAULTIN (5U) /*!< Bit position for FTM_FMS_FAULTIN. */
3623 #define BM_FTM_FMS_FAULTIN (0x00000020U) /*!< Bit mask for FTM_FMS_FAULTIN. */
3624 #define BS_FTM_FMS_FAULTIN (1U) /*!< Bit field size in bits for FTM_FMS_FAULTIN. */
3626 /*! @brief Read current value of the FTM_FMS_FAULTIN field. */
3627 #define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
3631 * @name Register FTM_FMS, field WPEN[6] (RW)
3633 * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
3634 * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
3635 * WPDIS. Writing 0 to WPEN has no effect.
3638 * - 0 - Write protection is disabled. Write protected bits can be written.
3639 * - 1 - Write protection is enabled. Write protected bits cannot be written.
3642 #define BP_FTM_FMS_WPEN (6U) /*!< Bit position for FTM_FMS_WPEN. */
3643 #define BM_FTM_FMS_WPEN (0x00000040U) /*!< Bit mask for FTM_FMS_WPEN. */
3644 #define BS_FTM_FMS_WPEN (1U) /*!< Bit field size in bits for FTM_FMS_WPEN. */
3646 /*! @brief Read current value of the FTM_FMS_WPEN field. */
3647 #define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
3649 /*! @brief Format value for bitfield FTM_FMS_WPEN. */
3650 #define BF_FTM_FMS_WPEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_WPEN) & BM_FTM_FMS_WPEN)
3652 /*! @brief Set the WPEN field to a new value. */
3653 #define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
3657 * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
3659 * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
3660 * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
3661 * a 0 to FAULTF while there is no existing fault condition at the enabled fault
3662 * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
3663 * detected in an enabled fault input before the clearing sequence is completed, the
3664 * sequence is reset so FAULTF remains set after the clearing sequence is
3665 * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
3666 * are cleared individually.
3669 * - 0 - No fault condition was detected.
3670 * - 1 - A fault condition was detected.
3673 #define BP_FTM_FMS_FAULTF (7U) /*!< Bit position for FTM_FMS_FAULTF. */
3674 #define BM_FTM_FMS_FAULTF (0x00000080U) /*!< Bit mask for FTM_FMS_FAULTF. */
3675 #define BS_FTM_FMS_FAULTF (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF. */
3677 /*! @brief Read current value of the FTM_FMS_FAULTF field. */
3678 #define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
3680 /*! @brief Format value for bitfield FTM_FMS_FAULTF. */
3681 #define BF_FTM_FMS_FAULTF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF) & BM_FTM_FMS_FAULTF)
3683 /*! @brief Set the FAULTF field to a new value. */
3684 #define BW_FTM_FMS_FAULTF(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF) = (v))
3687 /*******************************************************************************
3688 * HW_FTM_FILTER - Input Capture Filter Control
3689 ******************************************************************************/
3692 * @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
3694 * Reset value: 0x00000000U
3696 * This register selects the filter value for the inputs of channels. Channels
3697 * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
3698 * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
3699 * in input modes. Failure to do this could result in a missing valid signal.
3701 typedef union _hw_ftm_filter
3704 struct _hw_ftm_filter_bitfields
3706 uint32_t CH0FVAL : 4; /*!< [3:0] Channel 0 Input Filter */
3707 uint32_t CH1FVAL : 4; /*!< [7:4] Channel 1 Input Filter */
3708 uint32_t CH2FVAL : 4; /*!< [11:8] Channel 2 Input Filter */
3709 uint32_t CH3FVAL : 4; /*!< [15:12] Channel 3 Input Filter */
3710 uint32_t RESERVED0 : 16; /*!< [31:16] */
3715 * @name Constants and macros for entire FTM_FILTER register
3718 #define HW_FTM_FILTER_ADDR(x) ((x) + 0x78U)
3720 #define HW_FTM_FILTER(x) (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x))
3721 #define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U)
3722 #define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v))
3723 #define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) | (v)))
3724 #define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
3725 #define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v)))
3729 * Constants & macros for individual FTM_FILTER bitfields
3733 * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
3735 * Selects the filter value for the channel input. The filter is disabled when
3736 * the value is zero.
3739 #define BP_FTM_FILTER_CH0FVAL (0U) /*!< Bit position for FTM_FILTER_CH0FVAL. */
3740 #define BM_FTM_FILTER_CH0FVAL (0x0000000FU) /*!< Bit mask for FTM_FILTER_CH0FVAL. */
3741 #define BS_FTM_FILTER_CH0FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH0FVAL. */
3743 /*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
3744 #define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
3746 /*! @brief Format value for bitfield FTM_FILTER_CH0FVAL. */
3747 #define BF_FTM_FILTER_CH0FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH0FVAL) & BM_FTM_FILTER_CH0FVAL)
3749 /*! @brief Set the CH0FVAL field to a new value. */
3750 #define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v)))
3754 * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
3756 * Selects the filter value for the channel input. The filter is disabled when
3757 * the value is zero.
3760 #define BP_FTM_FILTER_CH1FVAL (4U) /*!< Bit position for FTM_FILTER_CH1FVAL. */
3761 #define BM_FTM_FILTER_CH1FVAL (0x000000F0U) /*!< Bit mask for FTM_FILTER_CH1FVAL. */
3762 #define BS_FTM_FILTER_CH1FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH1FVAL. */
3764 /*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
3765 #define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
3767 /*! @brief Format value for bitfield FTM_FILTER_CH1FVAL. */
3768 #define BF_FTM_FILTER_CH1FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH1FVAL) & BM_FTM_FILTER_CH1FVAL)
3770 /*! @brief Set the CH1FVAL field to a new value. */
3771 #define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v)))
3775 * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
3777 * Selects the filter value for the channel input. The filter is disabled when
3778 * the value is zero.
3781 #define BP_FTM_FILTER_CH2FVAL (8U) /*!< Bit position for FTM_FILTER_CH2FVAL. */
3782 #define BM_FTM_FILTER_CH2FVAL (0x00000F00U) /*!< Bit mask for FTM_FILTER_CH2FVAL. */
3783 #define BS_FTM_FILTER_CH2FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH2FVAL. */
3785 /*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
3786 #define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
3788 /*! @brief Format value for bitfield FTM_FILTER_CH2FVAL. */
3789 #define BF_FTM_FILTER_CH2FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH2FVAL) & BM_FTM_FILTER_CH2FVAL)
3791 /*! @brief Set the CH2FVAL field to a new value. */
3792 #define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v)))
3796 * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
3798 * Selects the filter value for the channel input. The filter is disabled when
3799 * the value is zero.
3802 #define BP_FTM_FILTER_CH3FVAL (12U) /*!< Bit position for FTM_FILTER_CH3FVAL. */
3803 #define BM_FTM_FILTER_CH3FVAL (0x0000F000U) /*!< Bit mask for FTM_FILTER_CH3FVAL. */
3804 #define BS_FTM_FILTER_CH3FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH3FVAL. */
3806 /*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
3807 #define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
3809 /*! @brief Format value for bitfield FTM_FILTER_CH3FVAL. */
3810 #define BF_FTM_FILTER_CH3FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH3FVAL) & BM_FTM_FILTER_CH3FVAL)
3812 /*! @brief Set the CH3FVAL field to a new value. */
3813 #define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v)))
3816 /*******************************************************************************
3817 * HW_FTM_FLTCTRL - Fault Control
3818 ******************************************************************************/
3821 * @brief HW_FTM_FLTCTRL - Fault Control (RW)
3823 * Reset value: 0x00000000U
3825 * This register selects the filter value for the fault inputs, enables the
3826 * fault inputs and the fault inputs filter.
3828 typedef union _hw_ftm_fltctrl
3831 struct _hw_ftm_fltctrl_bitfields
3833 uint32_t FAULT0EN : 1; /*!< [0] Fault Input 0 Enable */
3834 uint32_t FAULT1EN : 1; /*!< [1] Fault Input 1 Enable */
3835 uint32_t FAULT2EN : 1; /*!< [2] Fault Input 2 Enable */
3836 uint32_t FAULT3EN : 1; /*!< [3] Fault Input 3 Enable */
3837 uint32_t FFLTR0EN : 1; /*!< [4] Fault Input 0 Filter Enable */
3838 uint32_t FFLTR1EN : 1; /*!< [5] Fault Input 1 Filter Enable */
3839 uint32_t FFLTR2EN : 1; /*!< [6] Fault Input 2 Filter Enable */
3840 uint32_t FFLTR3EN : 1; /*!< [7] Fault Input 3 Filter Enable */
3841 uint32_t FFVAL : 4; /*!< [11:8] Fault Input Filter */
3842 uint32_t RESERVED0 : 20; /*!< [31:12] */
3847 * @name Constants and macros for entire FTM_FLTCTRL register
3850 #define HW_FTM_FLTCTRL_ADDR(x) ((x) + 0x7CU)
3852 #define HW_FTM_FLTCTRL(x) (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x))
3853 #define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U)
3854 #define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v))
3855 #define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) | (v)))
3856 #define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
3857 #define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v)))
3861 * Constants & macros for individual FTM_FLTCTRL bitfields
3865 * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
3867 * Enables the fault input. This field is write protected. It can be written
3868 * only when MODE[WPDIS] = 1.
3871 * - 0 - Fault input is disabled.
3872 * - 1 - Fault input is enabled.
3875 #define BP_FTM_FLTCTRL_FAULT0EN (0U) /*!< Bit position for FTM_FLTCTRL_FAULT0EN. */
3876 #define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) /*!< Bit mask for FTM_FLTCTRL_FAULT0EN. */
3877 #define BS_FTM_FLTCTRL_FAULT0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN. */
3879 /*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
3880 #define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
3882 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN. */
3883 #define BF_FTM_FLTCTRL_FAULT0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT0EN) & BM_FTM_FLTCTRL_FAULT0EN)
3885 /*! @brief Set the FAULT0EN field to a new value. */
3886 #define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
3890 * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
3892 * Enables the fault input. This field is write protected. It can be written
3893 * only when MODE[WPDIS] = 1.
3896 * - 0 - Fault input is disabled.
3897 * - 1 - Fault input is enabled.
3900 #define BP_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit position for FTM_FLTCTRL_FAULT1EN. */
3901 #define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) /*!< Bit mask for FTM_FLTCTRL_FAULT1EN. */
3902 #define BS_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN. */
3904 /*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
3905 #define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
3907 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN. */
3908 #define BF_FTM_FLTCTRL_FAULT1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT1EN) & BM_FTM_FLTCTRL_FAULT1EN)
3910 /*! @brief Set the FAULT1EN field to a new value. */
3911 #define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
3915 * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
3917 * Enables the fault input. This field is write protected. It can be written
3918 * only when MODE[WPDIS] = 1.
3921 * - 0 - Fault input is disabled.
3922 * - 1 - Fault input is enabled.
3925 #define BP_FTM_FLTCTRL_FAULT2EN (2U) /*!< Bit position for FTM_FLTCTRL_FAULT2EN. */
3926 #define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) /*!< Bit mask for FTM_FLTCTRL_FAULT2EN. */
3927 #define BS_FTM_FLTCTRL_FAULT2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN. */
3929 /*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
3930 #define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
3932 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN. */
3933 #define BF_FTM_FLTCTRL_FAULT2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT2EN) & BM_FTM_FLTCTRL_FAULT2EN)
3935 /*! @brief Set the FAULT2EN field to a new value. */
3936 #define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
3940 * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
3942 * Enables the fault input. This field is write protected. It can be written
3943 * only when MODE[WPDIS] = 1.
3946 * - 0 - Fault input is disabled.
3947 * - 1 - Fault input is enabled.
3950 #define BP_FTM_FLTCTRL_FAULT3EN (3U) /*!< Bit position for FTM_FLTCTRL_FAULT3EN. */
3951 #define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) /*!< Bit mask for FTM_FLTCTRL_FAULT3EN. */
3952 #define BS_FTM_FLTCTRL_FAULT3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN. */
3954 /*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
3955 #define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
3957 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN. */
3958 #define BF_FTM_FLTCTRL_FAULT3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT3EN) & BM_FTM_FLTCTRL_FAULT3EN)
3960 /*! @brief Set the FAULT3EN field to a new value. */
3961 #define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
3965 * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
3967 * Enables the filter for the fault input. This field is write protected. It can
3968 * be written only when MODE[WPDIS] = 1.
3971 * - 0 - Fault input filter is disabled.
3972 * - 1 - Fault input filter is enabled.
3975 #define BP_FTM_FLTCTRL_FFLTR0EN (4U) /*!< Bit position for FTM_FLTCTRL_FFLTR0EN. */
3976 #define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) /*!< Bit mask for FTM_FLTCTRL_FFLTR0EN. */
3977 #define BS_FTM_FLTCTRL_FFLTR0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN. */
3979 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
3980 #define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
3982 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN. */
3983 #define BF_FTM_FLTCTRL_FFLTR0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR0EN) & BM_FTM_FLTCTRL_FFLTR0EN)
3985 /*! @brief Set the FFLTR0EN field to a new value. */
3986 #define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
3990 * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
3992 * Enables the filter for the fault input. This field is write protected. It can
3993 * be written only when MODE[WPDIS] = 1.
3996 * - 0 - Fault input filter is disabled.
3997 * - 1 - Fault input filter is enabled.
4000 #define BP_FTM_FLTCTRL_FFLTR1EN (5U) /*!< Bit position for FTM_FLTCTRL_FFLTR1EN. */
4001 #define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) /*!< Bit mask for FTM_FLTCTRL_FFLTR1EN. */
4002 #define BS_FTM_FLTCTRL_FFLTR1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN. */
4004 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
4005 #define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
4007 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN. */
4008 #define BF_FTM_FLTCTRL_FFLTR1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR1EN) & BM_FTM_FLTCTRL_FFLTR1EN)
4010 /*! @brief Set the FFLTR1EN field to a new value. */
4011 #define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
4015 * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
4017 * Enables the filter for the fault input. This field is write protected. It can
4018 * be written only when MODE[WPDIS] = 1.
4021 * - 0 - Fault input filter is disabled.
4022 * - 1 - Fault input filter is enabled.
4025 #define BP_FTM_FLTCTRL_FFLTR2EN (6U) /*!< Bit position for FTM_FLTCTRL_FFLTR2EN. */
4026 #define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) /*!< Bit mask for FTM_FLTCTRL_FFLTR2EN. */
4027 #define BS_FTM_FLTCTRL_FFLTR2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN. */
4029 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
4030 #define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
4032 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN. */
4033 #define BF_FTM_FLTCTRL_FFLTR2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR2EN) & BM_FTM_FLTCTRL_FFLTR2EN)
4035 /*! @brief Set the FFLTR2EN field to a new value. */
4036 #define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
4040 * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
4042 * Enables the filter for the fault input. This field is write protected. It can
4043 * be written only when MODE[WPDIS] = 1.
4046 * - 0 - Fault input filter is disabled.
4047 * - 1 - Fault input filter is enabled.
4050 #define BP_FTM_FLTCTRL_FFLTR3EN (7U) /*!< Bit position for FTM_FLTCTRL_FFLTR3EN. */
4051 #define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) /*!< Bit mask for FTM_FLTCTRL_FFLTR3EN. */
4052 #define BS_FTM_FLTCTRL_FFLTR3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN. */
4054 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
4055 #define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
4057 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN. */
4058 #define BF_FTM_FLTCTRL_FFLTR3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR3EN) & BM_FTM_FLTCTRL_FFLTR3EN)
4060 /*! @brief Set the FFLTR3EN field to a new value. */
4061 #define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
4065 * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
4067 * Selects the filter value for the fault inputs. The fault filter is disabled
4068 * when the value is zero. Writing to this field has immediate effect and must be
4069 * done only when the fault control or all fault inputs are disabled. Failure to
4070 * do this could result in a missing fault detection.
4073 #define BP_FTM_FLTCTRL_FFVAL (8U) /*!< Bit position for FTM_FLTCTRL_FFVAL. */
4074 #define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) /*!< Bit mask for FTM_FLTCTRL_FFVAL. */
4075 #define BS_FTM_FLTCTRL_FFVAL (4U) /*!< Bit field size in bits for FTM_FLTCTRL_FFVAL. */
4077 /*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
4078 #define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
4080 /*! @brief Format value for bitfield FTM_FLTCTRL_FFVAL. */
4081 #define BF_FTM_FLTCTRL_FFVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFVAL) & BM_FTM_FLTCTRL_FFVAL)
4083 /*! @brief Set the FFVAL field to a new value. */
4084 #define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v)))
4087 /*******************************************************************************
4088 * HW_FTM_QDCTRL - Quadrature Decoder Control And Status
4089 ******************************************************************************/
4092 * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
4094 * Reset value: 0x00000000U
4096 * This register has the control and status bits for the Quadrature Decoder mode.
4098 typedef union _hw_ftm_qdctrl
4101 struct _hw_ftm_qdctrl_bitfields
4103 uint32_t QUADEN : 1; /*!< [0] Quadrature Decoder Mode Enable */
4104 uint32_t TOFDIR : 1; /*!< [1] Timer Overflow Direction In Quadrature
4106 uint32_t QUADIR : 1; /*!< [2] FTM Counter Direction In Quadrature
4108 uint32_t QUADMODE : 1; /*!< [3] Quadrature Decoder Mode */
4109 uint32_t PHBPOL : 1; /*!< [4] Phase B Input Polarity */
4110 uint32_t PHAPOL : 1; /*!< [5] Phase A Input Polarity */
4111 uint32_t PHBFLTREN : 1; /*!< [6] Phase B Input Filter Enable */
4112 uint32_t PHAFLTREN : 1; /*!< [7] Phase A Input Filter Enable */
4113 uint32_t RESERVED0 : 24; /*!< [31:8] */
4118 * @name Constants and macros for entire FTM_QDCTRL register
4121 #define HW_FTM_QDCTRL_ADDR(x) ((x) + 0x80U)
4123 #define HW_FTM_QDCTRL(x) (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x))
4124 #define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U)
4125 #define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v))
4126 #define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) | (v)))
4127 #define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
4128 #define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v)))
4132 * Constants & macros for individual FTM_QDCTRL bitfields
4136 * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
4138 * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
4139 * signals control the FTM counter direction. The Quadrature Decoder mode has
4140 * precedence over the other modes. See #ModeSel1Table. This field is write protected.
4141 * It can be written only when MODE[WPDIS] = 1.
4144 * - 0 - Quadrature Decoder mode is disabled.
4145 * - 1 - Quadrature Decoder mode is enabled.
4148 #define BP_FTM_QDCTRL_QUADEN (0U) /*!< Bit position for FTM_QDCTRL_QUADEN. */
4149 #define BM_FTM_QDCTRL_QUADEN (0x00000001U) /*!< Bit mask for FTM_QDCTRL_QUADEN. */
4150 #define BS_FTM_QDCTRL_QUADEN (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADEN. */
4152 /*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
4153 #define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
4155 /*! @brief Format value for bitfield FTM_QDCTRL_QUADEN. */
4156 #define BF_FTM_QDCTRL_QUADEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADEN) & BM_FTM_QDCTRL_QUADEN)
4158 /*! @brief Set the QUADEN field to a new value. */
4159 #define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
4163 * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
4165 * Indicates if the TOF bit was set on the top or the bottom of counting.
4168 * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
4169 * decrement and FTM counter changes from its minimum value (CNTIN register) to
4170 * its maximum value (MOD register).
4171 * - 1 - TOF bit was set on the top of counting. There was an FTM counter
4172 * increment and FTM counter changes from its maximum value (MOD register) to its
4173 * minimum value (CNTIN register).
4176 #define BP_FTM_QDCTRL_TOFDIR (1U) /*!< Bit position for FTM_QDCTRL_TOFDIR. */
4177 #define BM_FTM_QDCTRL_TOFDIR (0x00000002U) /*!< Bit mask for FTM_QDCTRL_TOFDIR. */
4178 #define BS_FTM_QDCTRL_TOFDIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_TOFDIR. */
4180 /*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
4181 #define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
4185 * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
4187 * Indicates the counting direction.
4190 * - 0 - Counting direction is decreasing (FTM counter decrement).
4191 * - 1 - Counting direction is increasing (FTM counter increment).
4194 #define BP_FTM_QDCTRL_QUADIR (2U) /*!< Bit position for FTM_QDCTRL_QUADIR. */
4195 #define BM_FTM_QDCTRL_QUADIR (0x00000004U) /*!< Bit mask for FTM_QDCTRL_QUADIR. */
4196 #define BS_FTM_QDCTRL_QUADIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADIR. */
4198 /*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
4199 #define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
4203 * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
4205 * Selects the encoding mode used in the Quadrature Decoder mode.
4208 * - 0 - Phase A and phase B encoding mode.
4209 * - 1 - Count and direction encoding mode.
4212 #define BP_FTM_QDCTRL_QUADMODE (3U) /*!< Bit position for FTM_QDCTRL_QUADMODE. */
4213 #define BM_FTM_QDCTRL_QUADMODE (0x00000008U) /*!< Bit mask for FTM_QDCTRL_QUADMODE. */
4214 #define BS_FTM_QDCTRL_QUADMODE (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADMODE. */
4216 /*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
4217 #define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
4219 /*! @brief Format value for bitfield FTM_QDCTRL_QUADMODE. */
4220 #define BF_FTM_QDCTRL_QUADMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADMODE) & BM_FTM_QDCTRL_QUADMODE)
4222 /*! @brief Set the QUADMODE field to a new value. */
4223 #define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
4227 * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
4229 * Selects the polarity for the quadrature decoder phase B input.
4232 * - 0 - Normal polarity. Phase B input signal is not inverted before
4233 * identifying the rising and falling edges of this signal.
4234 * - 1 - Inverted polarity. Phase B input signal is inverted before identifying
4235 * the rising and falling edges of this signal.
4238 #define BP_FTM_QDCTRL_PHBPOL (4U) /*!< Bit position for FTM_QDCTRL_PHBPOL. */
4239 #define BM_FTM_QDCTRL_PHBPOL (0x00000010U) /*!< Bit mask for FTM_QDCTRL_PHBPOL. */
4240 #define BS_FTM_QDCTRL_PHBPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBPOL. */
4242 /*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
4243 #define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
4245 /*! @brief Format value for bitfield FTM_QDCTRL_PHBPOL. */
4246 #define BF_FTM_QDCTRL_PHBPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBPOL) & BM_FTM_QDCTRL_PHBPOL)
4248 /*! @brief Set the PHBPOL field to a new value. */
4249 #define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
4253 * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
4255 * Selects the polarity for the quadrature decoder phase A input.
4258 * - 0 - Normal polarity. Phase A input signal is not inverted before
4259 * identifying the rising and falling edges of this signal.
4260 * - 1 - Inverted polarity. Phase A input signal is inverted before identifying
4261 * the rising and falling edges of this signal.
4264 #define BP_FTM_QDCTRL_PHAPOL (5U) /*!< Bit position for FTM_QDCTRL_PHAPOL. */
4265 #define BM_FTM_QDCTRL_PHAPOL (0x00000020U) /*!< Bit mask for FTM_QDCTRL_PHAPOL. */
4266 #define BS_FTM_QDCTRL_PHAPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAPOL. */
4268 /*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
4269 #define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
4271 /*! @brief Format value for bitfield FTM_QDCTRL_PHAPOL. */
4272 #define BF_FTM_QDCTRL_PHAPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAPOL) & BM_FTM_QDCTRL_PHAPOL)
4274 /*! @brief Set the PHAPOL field to a new value. */
4275 #define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
4279 * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
4281 * Enables the filter for the quadrature decoder phase B input. The filter value
4282 * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
4283 * filter is also disabled when CH1FVAL is zero.
4286 * - 0 - Phase B input filter is disabled.
4287 * - 1 - Phase B input filter is enabled.
4290 #define BP_FTM_QDCTRL_PHBFLTREN (6U) /*!< Bit position for FTM_QDCTRL_PHBFLTREN. */
4291 #define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) /*!< Bit mask for FTM_QDCTRL_PHBFLTREN. */
4292 #define BS_FTM_QDCTRL_PHBFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN. */
4294 /*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
4295 #define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
4297 /*! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN. */
4298 #define BF_FTM_QDCTRL_PHBFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBFLTREN) & BM_FTM_QDCTRL_PHBFLTREN)
4300 /*! @brief Set the PHBFLTREN field to a new value. */
4301 #define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
4305 * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
4307 * Enables the filter for the quadrature decoder phase A input. The filter value
4308 * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
4309 * filter is also disabled when CH0FVAL is zero.
4312 * - 0 - Phase A input filter is disabled.
4313 * - 1 - Phase A input filter is enabled.
4316 #define BP_FTM_QDCTRL_PHAFLTREN (7U) /*!< Bit position for FTM_QDCTRL_PHAFLTREN. */
4317 #define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) /*!< Bit mask for FTM_QDCTRL_PHAFLTREN. */
4318 #define BS_FTM_QDCTRL_PHAFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN. */
4320 /*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
4321 #define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
4323 /*! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN. */
4324 #define BF_FTM_QDCTRL_PHAFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAFLTREN) & BM_FTM_QDCTRL_PHAFLTREN)
4326 /*! @brief Set the PHAFLTREN field to a new value. */
4327 #define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
4330 /*******************************************************************************
4331 * HW_FTM_CONF - Configuration
4332 ******************************************************************************/
4335 * @brief HW_FTM_CONF - Configuration (RW)
4337 * Reset value: 0x00000000U
4339 * This register selects the number of times that the FTM counter overflow
4340 * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
4341 * of an external global time base, and the global time base signal generation.
4343 typedef union _hw_ftm_conf
4346 struct _hw_ftm_conf_bitfields
4348 uint32_t NUMTOF : 5; /*!< [4:0] TOF Frequency */
4349 uint32_t RESERVED0 : 1; /*!< [5] */
4350 uint32_t BDMMODE : 2; /*!< [7:6] BDM Mode */
4351 uint32_t RESERVED1 : 1; /*!< [8] */
4352 uint32_t GTBEEN : 1; /*!< [9] Global Time Base Enable */
4353 uint32_t GTBEOUT : 1; /*!< [10] Global Time Base Output */
4354 uint32_t RESERVED2 : 21; /*!< [31:11] */
4359 * @name Constants and macros for entire FTM_CONF register
4362 #define HW_FTM_CONF_ADDR(x) ((x) + 0x84U)
4364 #define HW_FTM_CONF(x) (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x))
4365 #define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U)
4366 #define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v))
4367 #define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) | (v)))
4368 #define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
4369 #define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v)))
4373 * Constants & macros for individual FTM_CONF bitfields
4377 * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
4379 * Selects the ratio between the number of counter overflows to the number of
4380 * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
4381 * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
4382 * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
4383 * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
4384 * first counter overflow but not for the next 3 overflows. This pattern continues
4385 * up to a maximum of 31.
4388 #define BP_FTM_CONF_NUMTOF (0U) /*!< Bit position for FTM_CONF_NUMTOF. */
4389 #define BM_FTM_CONF_NUMTOF (0x0000001FU) /*!< Bit mask for FTM_CONF_NUMTOF. */
4390 #define BS_FTM_CONF_NUMTOF (5U) /*!< Bit field size in bits for FTM_CONF_NUMTOF. */
4392 /*! @brief Read current value of the FTM_CONF_NUMTOF field. */
4393 #define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
4395 /*! @brief Format value for bitfield FTM_CONF_NUMTOF. */
4396 #define BF_FTM_CONF_NUMTOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_NUMTOF) & BM_FTM_CONF_NUMTOF)
4398 /*! @brief Set the NUMTOF field to a new value. */
4399 #define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v)))
4403 * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
4405 * Selects the FTM behavior in BDM mode. See BDM mode.
4408 #define BP_FTM_CONF_BDMMODE (6U) /*!< Bit position for FTM_CONF_BDMMODE. */
4409 #define BM_FTM_CONF_BDMMODE (0x000000C0U) /*!< Bit mask for FTM_CONF_BDMMODE. */
4410 #define BS_FTM_CONF_BDMMODE (2U) /*!< Bit field size in bits for FTM_CONF_BDMMODE. */
4412 /*! @brief Read current value of the FTM_CONF_BDMMODE field. */
4413 #define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
4415 /*! @brief Format value for bitfield FTM_CONF_BDMMODE. */
4416 #define BF_FTM_CONF_BDMMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_BDMMODE) & BM_FTM_CONF_BDMMODE)
4418 /*! @brief Set the BDMMODE field to a new value. */
4419 #define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v)))
4423 * @name Register FTM_CONF, field GTBEEN[9] (RW)
4425 * Configures the FTM to use an external global time base signal that is
4426 * generated by another FTM.
4429 * - 0 - Use of an external global time base is disabled.
4430 * - 1 - Use of an external global time base is enabled.
4433 #define BP_FTM_CONF_GTBEEN (9U) /*!< Bit position for FTM_CONF_GTBEEN. */
4434 #define BM_FTM_CONF_GTBEEN (0x00000200U) /*!< Bit mask for FTM_CONF_GTBEEN. */
4435 #define BS_FTM_CONF_GTBEEN (1U) /*!< Bit field size in bits for FTM_CONF_GTBEEN. */
4437 /*! @brief Read current value of the FTM_CONF_GTBEEN field. */
4438 #define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
4440 /*! @brief Format value for bitfield FTM_CONF_GTBEEN. */
4441 #define BF_FTM_CONF_GTBEEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEEN) & BM_FTM_CONF_GTBEEN)
4443 /*! @brief Set the GTBEEN field to a new value. */
4444 #define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
4448 * @name Register FTM_CONF, field GTBEOUT[10] (RW)
4450 * Enables the global time base signal generation to other FTMs.
4453 * - 0 - A global time base signal generation is disabled.
4454 * - 1 - A global time base signal generation is enabled.
4457 #define BP_FTM_CONF_GTBEOUT (10U) /*!< Bit position for FTM_CONF_GTBEOUT. */
4458 #define BM_FTM_CONF_GTBEOUT (0x00000400U) /*!< Bit mask for FTM_CONF_GTBEOUT. */
4459 #define BS_FTM_CONF_GTBEOUT (1U) /*!< Bit field size in bits for FTM_CONF_GTBEOUT. */
4461 /*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
4462 #define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
4464 /*! @brief Format value for bitfield FTM_CONF_GTBEOUT. */
4465 #define BF_FTM_CONF_GTBEOUT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEOUT) & BM_FTM_CONF_GTBEOUT)
4467 /*! @brief Set the GTBEOUT field to a new value. */
4468 #define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
4471 /*******************************************************************************
4472 * HW_FTM_FLTPOL - FTM Fault Input Polarity
4473 ******************************************************************************/
4476 * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
4478 * Reset value: 0x00000000U
4480 * This register defines the fault inputs polarity.
4482 typedef union _hw_ftm_fltpol
4485 struct _hw_ftm_fltpol_bitfields
4487 uint32_t FLT0POL : 1; /*!< [0] Fault Input 0 Polarity */
4488 uint32_t FLT1POL : 1; /*!< [1] Fault Input 1 Polarity */
4489 uint32_t FLT2POL : 1; /*!< [2] Fault Input 2 Polarity */
4490 uint32_t FLT3POL : 1; /*!< [3] Fault Input 3 Polarity */
4491 uint32_t RESERVED0 : 28; /*!< [31:4] */
4496 * @name Constants and macros for entire FTM_FLTPOL register
4499 #define HW_FTM_FLTPOL_ADDR(x) ((x) + 0x88U)
4501 #define HW_FTM_FLTPOL(x) (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x))
4502 #define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U)
4503 #define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v))
4504 #define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) | (v)))
4505 #define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
4506 #define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v)))
4510 * Constants & macros for individual FTM_FLTPOL bitfields
4514 * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
4516 * Defines the polarity of the fault input. This field is write protected. It
4517 * can be written only when MODE[WPDIS] = 1.
4520 * - 0 - The fault input polarity is active high. A 1 at the fault input
4521 * indicates a fault.
4522 * - 1 - The fault input polarity is active low. A 0 at the fault input
4523 * indicates a fault.
4526 #define BP_FTM_FLTPOL_FLT0POL (0U) /*!< Bit position for FTM_FLTPOL_FLT0POL. */
4527 #define BM_FTM_FLTPOL_FLT0POL (0x00000001U) /*!< Bit mask for FTM_FLTPOL_FLT0POL. */
4528 #define BS_FTM_FLTPOL_FLT0POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT0POL. */
4530 /*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
4531 #define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
4533 /*! @brief Format value for bitfield FTM_FLTPOL_FLT0POL. */
4534 #define BF_FTM_FLTPOL_FLT0POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT0POL) & BM_FTM_FLTPOL_FLT0POL)
4536 /*! @brief Set the FLT0POL field to a new value. */
4537 #define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
4541 * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
4543 * Defines the polarity of the fault input. This field is write protected. It
4544 * can be written only when MODE[WPDIS] = 1.
4547 * - 0 - The fault input polarity is active high. A 1 at the fault input
4548 * indicates a fault.
4549 * - 1 - The fault input polarity is active low. A 0 at the fault input
4550 * indicates a fault.
4553 #define BP_FTM_FLTPOL_FLT1POL (1U) /*!< Bit position for FTM_FLTPOL_FLT1POL. */
4554 #define BM_FTM_FLTPOL_FLT1POL (0x00000002U) /*!< Bit mask for FTM_FLTPOL_FLT1POL. */
4555 #define BS_FTM_FLTPOL_FLT1POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT1POL. */
4557 /*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
4558 #define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
4560 /*! @brief Format value for bitfield FTM_FLTPOL_FLT1POL. */
4561 #define BF_FTM_FLTPOL_FLT1POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT1POL) & BM_FTM_FLTPOL_FLT1POL)
4563 /*! @brief Set the FLT1POL field to a new value. */
4564 #define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
4568 * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
4570 * Defines the polarity of the fault input. This field is write protected. It
4571 * can be written only when MODE[WPDIS] = 1.
4574 * - 0 - The fault input polarity is active high. A 1 at the fault input
4575 * indicates a fault.
4576 * - 1 - The fault input polarity is active low. A 0 at the fault input
4577 * indicates a fault.
4580 #define BP_FTM_FLTPOL_FLT2POL (2U) /*!< Bit position for FTM_FLTPOL_FLT2POL. */
4581 #define BM_FTM_FLTPOL_FLT2POL (0x00000004U) /*!< Bit mask for FTM_FLTPOL_FLT2POL. */
4582 #define BS_FTM_FLTPOL_FLT2POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT2POL. */
4584 /*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
4585 #define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
4587 /*! @brief Format value for bitfield FTM_FLTPOL_FLT2POL. */
4588 #define BF_FTM_FLTPOL_FLT2POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT2POL) & BM_FTM_FLTPOL_FLT2POL)
4590 /*! @brief Set the FLT2POL field to a new value. */
4591 #define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
4595 * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
4597 * Defines the polarity of the fault input. This field is write protected. It
4598 * can be written only when MODE[WPDIS] = 1.
4601 * - 0 - The fault input polarity is active high. A 1 at the fault input
4602 * indicates a fault.
4603 * - 1 - The fault input polarity is active low. A 0 at the fault input
4604 * indicates a fault.
4607 #define BP_FTM_FLTPOL_FLT3POL (3U) /*!< Bit position for FTM_FLTPOL_FLT3POL. */
4608 #define BM_FTM_FLTPOL_FLT3POL (0x00000008U) /*!< Bit mask for FTM_FLTPOL_FLT3POL. */
4609 #define BS_FTM_FLTPOL_FLT3POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT3POL. */
4611 /*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
4612 #define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
4614 /*! @brief Format value for bitfield FTM_FLTPOL_FLT3POL. */
4615 #define BF_FTM_FLTPOL_FLT3POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT3POL) & BM_FTM_FLTPOL_FLT3POL)
4617 /*! @brief Set the FLT3POL field to a new value. */
4618 #define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
4621 /*******************************************************************************
4622 * HW_FTM_SYNCONF - Synchronization Configuration
4623 ******************************************************************************/
4626 * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
4628 * Reset value: 0x00000000U
4630 * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
4631 * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
4632 * 0, 1, 2, when the hardware trigger j is detected.
4634 typedef union _hw_ftm_synconf
4637 struct _hw_ftm_synconf_bitfields
4639 uint32_t HWTRIGMODE : 1; /*!< [0] Hardware Trigger Mode */
4640 uint32_t RESERVED0 : 1; /*!< [1] */
4641 uint32_t CNTINC : 1; /*!< [2] CNTIN Register Synchronization */
4642 uint32_t RESERVED1 : 1; /*!< [3] */
4643 uint32_t INVC : 1; /*!< [4] INVCTRL Register Synchronization */
4644 uint32_t SWOC : 1; /*!< [5] SWOCTRL Register Synchronization */
4645 uint32_t RESERVED2 : 1; /*!< [6] */
4646 uint32_t SYNCMODE : 1; /*!< [7] Synchronization Mode */
4647 uint32_t SWRSTCNT : 1; /*!< [8] */
4648 uint32_t SWWRBUF : 1; /*!< [9] */
4649 uint32_t SWOM : 1; /*!< [10] */
4650 uint32_t SWINVC : 1; /*!< [11] */
4651 uint32_t SWSOC : 1; /*!< [12] */
4652 uint32_t RESERVED3 : 3; /*!< [15:13] */
4653 uint32_t HWRSTCNT : 1; /*!< [16] */
4654 uint32_t HWWRBUF : 1; /*!< [17] */
4655 uint32_t HWOM : 1; /*!< [18] */
4656 uint32_t HWINVC : 1; /*!< [19] */
4657 uint32_t HWSOC : 1; /*!< [20] */
4658 uint32_t RESERVED4 : 11; /*!< [31:21] */
4663 * @name Constants and macros for entire FTM_SYNCONF register
4666 #define HW_FTM_SYNCONF_ADDR(x) ((x) + 0x8CU)
4668 #define HW_FTM_SYNCONF(x) (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x))
4669 #define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U)
4670 #define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v))
4671 #define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) | (v)))
4672 #define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
4673 #define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v)))
4677 * Constants & macros for individual FTM_SYNCONF bitfields
4681 * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
4684 * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
4686 * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
4687 * detected, where j = 0, 1,2.
4690 #define BP_FTM_SYNCONF_HWTRIGMODE (0U) /*!< Bit position for FTM_SYNCONF_HWTRIGMODE. */
4691 #define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) /*!< Bit mask for FTM_SYNCONF_HWTRIGMODE. */
4692 #define BS_FTM_SYNCONF_HWTRIGMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE. */
4694 /*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
4695 #define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
4697 /*! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE. */
4698 #define BF_FTM_SYNCONF_HWTRIGMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWTRIGMODE) & BM_FTM_SYNCONF_HWTRIGMODE)
4700 /*! @brief Set the HWTRIGMODE field to a new value. */
4701 #define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
4705 * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
4708 * - 0 - CNTIN register is updated with its buffer value at all rising edges of
4710 * - 1 - CNTIN register is updated with its buffer value by the PWM
4714 #define BP_FTM_SYNCONF_CNTINC (2U) /*!< Bit position for FTM_SYNCONF_CNTINC. */
4715 #define BM_FTM_SYNCONF_CNTINC (0x00000004U) /*!< Bit mask for FTM_SYNCONF_CNTINC. */
4716 #define BS_FTM_SYNCONF_CNTINC (1U) /*!< Bit field size in bits for FTM_SYNCONF_CNTINC. */
4718 /*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
4719 #define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
4721 /*! @brief Format value for bitfield FTM_SYNCONF_CNTINC. */
4722 #define BF_FTM_SYNCONF_CNTINC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_CNTINC) & BM_FTM_SYNCONF_CNTINC)
4724 /*! @brief Set the CNTINC field to a new value. */
4725 #define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
4729 * @name Register FTM_SYNCONF, field INVC[4] (RW)
4732 * - 0 - INVCTRL register is updated with its buffer value at all rising edges
4734 * - 1 - INVCTRL register is updated with its buffer value by the PWM
4738 #define BP_FTM_SYNCONF_INVC (4U) /*!< Bit position for FTM_SYNCONF_INVC. */
4739 #define BM_FTM_SYNCONF_INVC (0x00000010U) /*!< Bit mask for FTM_SYNCONF_INVC. */
4740 #define BS_FTM_SYNCONF_INVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_INVC. */
4742 /*! @brief Read current value of the FTM_SYNCONF_INVC field. */
4743 #define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
4745 /*! @brief Format value for bitfield FTM_SYNCONF_INVC. */
4746 #define BF_FTM_SYNCONF_INVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_INVC) & BM_FTM_SYNCONF_INVC)
4748 /*! @brief Set the INVC field to a new value. */
4749 #define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
4753 * @name Register FTM_SYNCONF, field SWOC[5] (RW)
4756 * - 0 - SWOCTRL register is updated with its buffer value at all rising edges
4758 * - 1 - SWOCTRL register is updated with its buffer value by the PWM
4762 #define BP_FTM_SYNCONF_SWOC (5U) /*!< Bit position for FTM_SYNCONF_SWOC. */
4763 #define BM_FTM_SYNCONF_SWOC (0x00000020U) /*!< Bit mask for FTM_SYNCONF_SWOC. */
4764 #define BS_FTM_SYNCONF_SWOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOC. */
4766 /*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
4767 #define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
4769 /*! @brief Format value for bitfield FTM_SYNCONF_SWOC. */
4770 #define BF_FTM_SYNCONF_SWOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOC) & BM_FTM_SYNCONF_SWOC)
4772 /*! @brief Set the SWOC field to a new value. */
4773 #define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
4777 * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
4779 * Selects the PWM Synchronization mode.
4782 * - 0 - Legacy PWM synchronization is selected.
4783 * - 1 - Enhanced PWM synchronization is selected.
4786 #define BP_FTM_SYNCONF_SYNCMODE (7U) /*!< Bit position for FTM_SYNCONF_SYNCMODE. */
4787 #define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) /*!< Bit mask for FTM_SYNCONF_SYNCMODE. */
4788 #define BS_FTM_SYNCONF_SYNCMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_SYNCMODE. */
4790 /*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
4791 #define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
4793 /*! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE. */
4794 #define BF_FTM_SYNCONF_SYNCMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SYNCMODE) & BM_FTM_SYNCONF_SYNCMODE)
4796 /*! @brief Set the SYNCMODE field to a new value. */
4797 #define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
4801 * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
4803 * FTM counter synchronization is activated by the software trigger.
4806 * - 0 - The software trigger does not activate the FTM counter synchronization.
4807 * - 1 - The software trigger activates the FTM counter synchronization.
4810 #define BP_FTM_SYNCONF_SWRSTCNT (8U) /*!< Bit position for FTM_SYNCONF_SWRSTCNT. */
4811 #define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) /*!< Bit mask for FTM_SYNCONF_SWRSTCNT. */
4812 #define BS_FTM_SYNCONF_SWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT. */
4814 /*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
4815 #define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
4817 /*! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT. */
4818 #define BF_FTM_SYNCONF_SWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWRSTCNT) & BM_FTM_SYNCONF_SWRSTCNT)
4820 /*! @brief Set the SWRSTCNT field to a new value. */
4821 #define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
4825 * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
4827 * MOD, CNTIN, and CV registers synchronization is activated by the software
4831 * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
4833 * - 1 - The software trigger activates MOD, CNTIN, and CV registers
4837 #define BP_FTM_SYNCONF_SWWRBUF (9U) /*!< Bit position for FTM_SYNCONF_SWWRBUF. */
4838 #define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) /*!< Bit mask for FTM_SYNCONF_SWWRBUF. */
4839 #define BS_FTM_SYNCONF_SWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWWRBUF. */
4841 /*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
4842 #define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
4844 /*! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF. */
4845 #define BF_FTM_SYNCONF_SWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWWRBUF) & BM_FTM_SYNCONF_SWWRBUF)
4847 /*! @brief Set the SWWRBUF field to a new value. */
4848 #define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
4852 * @name Register FTM_SYNCONF, field SWOM[10] (RW)
4854 * Output mask synchronization is activated by the software trigger.
4857 * - 0 - The software trigger does not activate the OUTMASK register
4859 * - 1 - The software trigger activates the OUTMASK register synchronization.
4862 #define BP_FTM_SYNCONF_SWOM (10U) /*!< Bit position for FTM_SYNCONF_SWOM. */
4863 #define BM_FTM_SYNCONF_SWOM (0x00000400U) /*!< Bit mask for FTM_SYNCONF_SWOM. */
4864 #define BS_FTM_SYNCONF_SWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOM. */
4866 /*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
4867 #define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
4869 /*! @brief Format value for bitfield FTM_SYNCONF_SWOM. */
4870 #define BF_FTM_SYNCONF_SWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOM) & BM_FTM_SYNCONF_SWOM)
4872 /*! @brief Set the SWOM field to a new value. */
4873 #define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
4877 * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
4879 * Inverting control synchronization is activated by the software trigger.
4882 * - 0 - The software trigger does not activate the INVCTRL register
4884 * - 1 - The software trigger activates the INVCTRL register synchronization.
4887 #define BP_FTM_SYNCONF_SWINVC (11U) /*!< Bit position for FTM_SYNCONF_SWINVC. */
4888 #define BM_FTM_SYNCONF_SWINVC (0x00000800U) /*!< Bit mask for FTM_SYNCONF_SWINVC. */
4889 #define BS_FTM_SYNCONF_SWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWINVC. */
4891 /*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
4892 #define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
4894 /*! @brief Format value for bitfield FTM_SYNCONF_SWINVC. */
4895 #define BF_FTM_SYNCONF_SWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWINVC) & BM_FTM_SYNCONF_SWINVC)
4897 /*! @brief Set the SWINVC field to a new value. */
4898 #define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
4902 * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
4904 * Software output control synchronization is activated by the software trigger.
4907 * - 0 - The software trigger does not activate the SWOCTRL register
4909 * - 1 - The software trigger activates the SWOCTRL register synchronization.
4912 #define BP_FTM_SYNCONF_SWSOC (12U) /*!< Bit position for FTM_SYNCONF_SWSOC. */
4913 #define BM_FTM_SYNCONF_SWSOC (0x00001000U) /*!< Bit mask for FTM_SYNCONF_SWSOC. */
4914 #define BS_FTM_SYNCONF_SWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWSOC. */
4916 /*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
4917 #define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
4919 /*! @brief Format value for bitfield FTM_SYNCONF_SWSOC. */
4920 #define BF_FTM_SYNCONF_SWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWSOC) & BM_FTM_SYNCONF_SWSOC)
4922 /*! @brief Set the SWSOC field to a new value. */
4923 #define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
4927 * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
4929 * FTM counter synchronization is activated by a hardware trigger.
4932 * - 0 - A hardware trigger does not activate the FTM counter synchronization.
4933 * - 1 - A hardware trigger activates the FTM counter synchronization.
4936 #define BP_FTM_SYNCONF_HWRSTCNT (16U) /*!< Bit position for FTM_SYNCONF_HWRSTCNT. */
4937 #define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) /*!< Bit mask for FTM_SYNCONF_HWRSTCNT. */
4938 #define BS_FTM_SYNCONF_HWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT. */
4940 /*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
4941 #define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
4943 /*! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT. */
4944 #define BF_FTM_SYNCONF_HWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWRSTCNT) & BM_FTM_SYNCONF_HWRSTCNT)
4946 /*! @brief Set the HWRSTCNT field to a new value. */
4947 #define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
4951 * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
4953 * MOD, CNTIN, and CV registers synchronization is activated by a hardware
4957 * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
4959 * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
4963 #define BP_FTM_SYNCONF_HWWRBUF (17U) /*!< Bit position for FTM_SYNCONF_HWWRBUF. */
4964 #define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) /*!< Bit mask for FTM_SYNCONF_HWWRBUF. */
4965 #define BS_FTM_SYNCONF_HWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWWRBUF. */
4967 /*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
4968 #define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
4970 /*! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF. */
4971 #define BF_FTM_SYNCONF_HWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWWRBUF) & BM_FTM_SYNCONF_HWWRBUF)
4973 /*! @brief Set the HWWRBUF field to a new value. */
4974 #define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
4978 * @name Register FTM_SYNCONF, field HWOM[18] (RW)
4980 * Output mask synchronization is activated by a hardware trigger.
4983 * - 0 - A hardware trigger does not activate the OUTMASK register
4985 * - 1 - A hardware trigger activates the OUTMASK register synchronization.
4988 #define BP_FTM_SYNCONF_HWOM (18U) /*!< Bit position for FTM_SYNCONF_HWOM. */
4989 #define BM_FTM_SYNCONF_HWOM (0x00040000U) /*!< Bit mask for FTM_SYNCONF_HWOM. */
4990 #define BS_FTM_SYNCONF_HWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWOM. */
4992 /*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
4993 #define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
4995 /*! @brief Format value for bitfield FTM_SYNCONF_HWOM. */
4996 #define BF_FTM_SYNCONF_HWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWOM) & BM_FTM_SYNCONF_HWOM)
4998 /*! @brief Set the HWOM field to a new value. */
4999 #define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
5003 * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
5005 * Inverting control synchronization is activated by a hardware trigger.
5008 * - 0 - A hardware trigger does not activate the INVCTRL register
5010 * - 1 - A hardware trigger activates the INVCTRL register synchronization.
5013 #define BP_FTM_SYNCONF_HWINVC (19U) /*!< Bit position for FTM_SYNCONF_HWINVC. */
5014 #define BM_FTM_SYNCONF_HWINVC (0x00080000U) /*!< Bit mask for FTM_SYNCONF_HWINVC. */
5015 #define BS_FTM_SYNCONF_HWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWINVC. */
5017 /*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
5018 #define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
5020 /*! @brief Format value for bitfield FTM_SYNCONF_HWINVC. */
5021 #define BF_FTM_SYNCONF_HWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWINVC) & BM_FTM_SYNCONF_HWINVC)
5023 /*! @brief Set the HWINVC field to a new value. */
5024 #define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
5028 * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
5030 * Software output control synchronization is activated by a hardware trigger.
5033 * - 0 - A hardware trigger does not activate the SWOCTRL register
5035 * - 1 - A hardware trigger activates the SWOCTRL register synchronization.
5038 #define BP_FTM_SYNCONF_HWSOC (20U) /*!< Bit position for FTM_SYNCONF_HWSOC. */
5039 #define BM_FTM_SYNCONF_HWSOC (0x00100000U) /*!< Bit mask for FTM_SYNCONF_HWSOC. */
5040 #define BS_FTM_SYNCONF_HWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWSOC. */
5042 /*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
5043 #define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
5045 /*! @brief Format value for bitfield FTM_SYNCONF_HWSOC. */
5046 #define BF_FTM_SYNCONF_HWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWSOC) & BM_FTM_SYNCONF_HWSOC)
5048 /*! @brief Set the HWSOC field to a new value. */
5049 #define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
5052 /*******************************************************************************
5053 * HW_FTM_INVCTRL - FTM Inverting Control
5054 ******************************************************************************/
5057 * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
5059 * Reset value: 0x00000000U
5061 * This register controls when the channel (n) output becomes the channel (n+1)
5062 * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
5063 * bit enables the inverting operation for the corresponding pair channels m. This
5064 * register has a write buffer. The INVmEN bit is updated by the INVCTRL
5065 * register synchronization.
5067 typedef union _hw_ftm_invctrl
5070 struct _hw_ftm_invctrl_bitfields
5072 uint32_t INV0EN : 1; /*!< [0] Pair Channels 0 Inverting Enable */
5073 uint32_t INV1EN : 1; /*!< [1] Pair Channels 1 Inverting Enable */
5074 uint32_t INV2EN : 1; /*!< [2] Pair Channels 2 Inverting Enable */
5075 uint32_t INV3EN : 1; /*!< [3] Pair Channels 3 Inverting Enable */
5076 uint32_t RESERVED0 : 28; /*!< [31:4] */
5081 * @name Constants and macros for entire FTM_INVCTRL register
5084 #define HW_FTM_INVCTRL_ADDR(x) ((x) + 0x90U)
5086 #define HW_FTM_INVCTRL(x) (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x))
5087 #define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U)
5088 #define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v))
5089 #define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) | (v)))
5090 #define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
5091 #define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v)))
5095 * Constants & macros for individual FTM_INVCTRL bitfields
5099 * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
5102 * - 0 - Inverting is disabled.
5103 * - 1 - Inverting is enabled.
5106 #define BP_FTM_INVCTRL_INV0EN (0U) /*!< Bit position for FTM_INVCTRL_INV0EN. */
5107 #define BM_FTM_INVCTRL_INV0EN (0x00000001U) /*!< Bit mask for FTM_INVCTRL_INV0EN. */
5108 #define BS_FTM_INVCTRL_INV0EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV0EN. */
5110 /*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
5111 #define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
5113 /*! @brief Format value for bitfield FTM_INVCTRL_INV0EN. */
5114 #define BF_FTM_INVCTRL_INV0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV0EN) & BM_FTM_INVCTRL_INV0EN)
5116 /*! @brief Set the INV0EN field to a new value. */
5117 #define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
5121 * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
5124 * - 0 - Inverting is disabled.
5125 * - 1 - Inverting is enabled.
5128 #define BP_FTM_INVCTRL_INV1EN (1U) /*!< Bit position for FTM_INVCTRL_INV1EN. */
5129 #define BM_FTM_INVCTRL_INV1EN (0x00000002U) /*!< Bit mask for FTM_INVCTRL_INV1EN. */
5130 #define BS_FTM_INVCTRL_INV1EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV1EN. */
5132 /*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
5133 #define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
5135 /*! @brief Format value for bitfield FTM_INVCTRL_INV1EN. */
5136 #define BF_FTM_INVCTRL_INV1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV1EN) & BM_FTM_INVCTRL_INV1EN)
5138 /*! @brief Set the INV1EN field to a new value. */
5139 #define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
5143 * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
5146 * - 0 - Inverting is disabled.
5147 * - 1 - Inverting is enabled.
5150 #define BP_FTM_INVCTRL_INV2EN (2U) /*!< Bit position for FTM_INVCTRL_INV2EN. */
5151 #define BM_FTM_INVCTRL_INV2EN (0x00000004U) /*!< Bit mask for FTM_INVCTRL_INV2EN. */
5152 #define BS_FTM_INVCTRL_INV2EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV2EN. */
5154 /*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
5155 #define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
5157 /*! @brief Format value for bitfield FTM_INVCTRL_INV2EN. */
5158 #define BF_FTM_INVCTRL_INV2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV2EN) & BM_FTM_INVCTRL_INV2EN)
5160 /*! @brief Set the INV2EN field to a new value. */
5161 #define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
5165 * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
5168 * - 0 - Inverting is disabled.
5169 * - 1 - Inverting is enabled.
5172 #define BP_FTM_INVCTRL_INV3EN (3U) /*!< Bit position for FTM_INVCTRL_INV3EN. */
5173 #define BM_FTM_INVCTRL_INV3EN (0x00000008U) /*!< Bit mask for FTM_INVCTRL_INV3EN. */
5174 #define BS_FTM_INVCTRL_INV3EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV3EN. */
5176 /*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
5177 #define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
5179 /*! @brief Format value for bitfield FTM_INVCTRL_INV3EN. */
5180 #define BF_FTM_INVCTRL_INV3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV3EN) & BM_FTM_INVCTRL_INV3EN)
5182 /*! @brief Set the INV3EN field to a new value. */
5183 #define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
5186 /*******************************************************************************
5187 * HW_FTM_SWOCTRL - FTM Software Output Control
5188 ******************************************************************************/
5191 * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
5193 * Reset value: 0x00000000U
5195 * This register enables software control of channel (n) output and defines the
5196 * value forced to the channel (n) output: The CHnOC bits enable the control of
5197 * the corresponding channel (n) output by software. The CHnOCV bits select the
5198 * value that is forced at the corresponding channel (n) output. This register has
5199 * a write buffer. The fields are updated by the SWOCTRL register synchronization.
5201 typedef union _hw_ftm_swoctrl
5204 struct _hw_ftm_swoctrl_bitfields
5206 uint32_t CH0OC : 1; /*!< [0] Channel 0 Software Output Control Enable
5208 uint32_t CH1OC : 1; /*!< [1] Channel 1 Software Output Control Enable
5210 uint32_t CH2OC : 1; /*!< [2] Channel 2 Software Output Control Enable
5212 uint32_t CH3OC : 1; /*!< [3] Channel 3 Software Output Control Enable
5214 uint32_t CH4OC : 1; /*!< [4] Channel 4 Software Output Control Enable
5216 uint32_t CH5OC : 1; /*!< [5] Channel 5 Software Output Control Enable
5218 uint32_t CH6OC : 1; /*!< [6] Channel 6 Software Output Control Enable
5220 uint32_t CH7OC : 1; /*!< [7] Channel 7 Software Output Control Enable
5222 uint32_t CH0OCV : 1; /*!< [8] Channel 0 Software Output Control Value
5224 uint32_t CH1OCV : 1; /*!< [9] Channel 1 Software Output Control Value
5226 uint32_t CH2OCV : 1; /*!< [10] Channel 2 Software Output Control
5228 uint32_t CH3OCV : 1; /*!< [11] Channel 3 Software Output Control
5230 uint32_t CH4OCV : 1; /*!< [12] Channel 4 Software Output Control
5232 uint32_t CH5OCV : 1; /*!< [13] Channel 5 Software Output Control
5234 uint32_t CH6OCV : 1; /*!< [14] Channel 6 Software Output Control
5236 uint32_t CH7OCV : 1; /*!< [15] Channel 7 Software Output Control
5238 uint32_t RESERVED0 : 16; /*!< [31:16] */
5243 * @name Constants and macros for entire FTM_SWOCTRL register
5246 #define HW_FTM_SWOCTRL_ADDR(x) ((x) + 0x94U)
5248 #define HW_FTM_SWOCTRL(x) (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x))
5249 #define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U)
5250 #define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v))
5251 #define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) | (v)))
5252 #define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
5253 #define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v)))
5257 * Constants & macros for individual FTM_SWOCTRL bitfields
5261 * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
5264 * - 0 - The channel output is not affected by software output control.
5265 * - 1 - The channel output is affected by software output control.
5268 #define BP_FTM_SWOCTRL_CH0OC (0U) /*!< Bit position for FTM_SWOCTRL_CH0OC. */
5269 #define BM_FTM_SWOCTRL_CH0OC (0x00000001U) /*!< Bit mask for FTM_SWOCTRL_CH0OC. */
5270 #define BS_FTM_SWOCTRL_CH0OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OC. */
5272 /*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
5273 #define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
5275 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OC. */
5276 #define BF_FTM_SWOCTRL_CH0OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OC) & BM_FTM_SWOCTRL_CH0OC)
5278 /*! @brief Set the CH0OC field to a new value. */
5279 #define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
5283 * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
5286 * - 0 - The channel output is not affected by software output control.
5287 * - 1 - The channel output is affected by software output control.
5290 #define BP_FTM_SWOCTRL_CH1OC (1U) /*!< Bit position for FTM_SWOCTRL_CH1OC. */
5291 #define BM_FTM_SWOCTRL_CH1OC (0x00000002U) /*!< Bit mask for FTM_SWOCTRL_CH1OC. */
5292 #define BS_FTM_SWOCTRL_CH1OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OC. */
5294 /*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
5295 #define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
5297 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OC. */
5298 #define BF_FTM_SWOCTRL_CH1OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OC) & BM_FTM_SWOCTRL_CH1OC)
5300 /*! @brief Set the CH1OC field to a new value. */
5301 #define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
5305 * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
5308 * - 0 - The channel output is not affected by software output control.
5309 * - 1 - The channel output is affected by software output control.
5312 #define BP_FTM_SWOCTRL_CH2OC (2U) /*!< Bit position for FTM_SWOCTRL_CH2OC. */
5313 #define BM_FTM_SWOCTRL_CH2OC (0x00000004U) /*!< Bit mask for FTM_SWOCTRL_CH2OC. */
5314 #define BS_FTM_SWOCTRL_CH2OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OC. */
5316 /*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
5317 #define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
5319 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OC. */
5320 #define BF_FTM_SWOCTRL_CH2OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OC) & BM_FTM_SWOCTRL_CH2OC)
5322 /*! @brief Set the CH2OC field to a new value. */
5323 #define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
5327 * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
5330 * - 0 - The channel output is not affected by software output control.
5331 * - 1 - The channel output is affected by software output control.
5334 #define BP_FTM_SWOCTRL_CH3OC (3U) /*!< Bit position for FTM_SWOCTRL_CH3OC. */
5335 #define BM_FTM_SWOCTRL_CH3OC (0x00000008U) /*!< Bit mask for FTM_SWOCTRL_CH3OC. */
5336 #define BS_FTM_SWOCTRL_CH3OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OC. */
5338 /*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
5339 #define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
5341 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OC. */
5342 #define BF_FTM_SWOCTRL_CH3OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OC) & BM_FTM_SWOCTRL_CH3OC)
5344 /*! @brief Set the CH3OC field to a new value. */
5345 #define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
5349 * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
5352 * - 0 - The channel output is not affected by software output control.
5353 * - 1 - The channel output is affected by software output control.
5356 #define BP_FTM_SWOCTRL_CH4OC (4U) /*!< Bit position for FTM_SWOCTRL_CH4OC. */
5357 #define BM_FTM_SWOCTRL_CH4OC (0x00000010U) /*!< Bit mask for FTM_SWOCTRL_CH4OC. */
5358 #define BS_FTM_SWOCTRL_CH4OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OC. */
5360 /*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
5361 #define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
5363 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OC. */
5364 #define BF_FTM_SWOCTRL_CH4OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OC) & BM_FTM_SWOCTRL_CH4OC)
5366 /*! @brief Set the CH4OC field to a new value. */
5367 #define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
5371 * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
5374 * - 0 - The channel output is not affected by software output control.
5375 * - 1 - The channel output is affected by software output control.
5378 #define BP_FTM_SWOCTRL_CH5OC (5U) /*!< Bit position for FTM_SWOCTRL_CH5OC. */
5379 #define BM_FTM_SWOCTRL_CH5OC (0x00000020U) /*!< Bit mask for FTM_SWOCTRL_CH5OC. */
5380 #define BS_FTM_SWOCTRL_CH5OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OC. */
5382 /*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
5383 #define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
5385 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OC. */
5386 #define BF_FTM_SWOCTRL_CH5OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OC) & BM_FTM_SWOCTRL_CH5OC)
5388 /*! @brief Set the CH5OC field to a new value. */
5389 #define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
5393 * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
5396 * - 0 - The channel output is not affected by software output control.
5397 * - 1 - The channel output is affected by software output control.
5400 #define BP_FTM_SWOCTRL_CH6OC (6U) /*!< Bit position for FTM_SWOCTRL_CH6OC. */
5401 #define BM_FTM_SWOCTRL_CH6OC (0x00000040U) /*!< Bit mask for FTM_SWOCTRL_CH6OC. */
5402 #define BS_FTM_SWOCTRL_CH6OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OC. */
5404 /*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
5405 #define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
5407 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OC. */
5408 #define BF_FTM_SWOCTRL_CH6OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OC) & BM_FTM_SWOCTRL_CH6OC)
5410 /*! @brief Set the CH6OC field to a new value. */
5411 #define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
5415 * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
5418 * - 0 - The channel output is not affected by software output control.
5419 * - 1 - The channel output is affected by software output control.
5422 #define BP_FTM_SWOCTRL_CH7OC (7U) /*!< Bit position for FTM_SWOCTRL_CH7OC. */
5423 #define BM_FTM_SWOCTRL_CH7OC (0x00000080U) /*!< Bit mask for FTM_SWOCTRL_CH7OC. */
5424 #define BS_FTM_SWOCTRL_CH7OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OC. */
5426 /*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
5427 #define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
5429 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OC. */
5430 #define BF_FTM_SWOCTRL_CH7OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OC) & BM_FTM_SWOCTRL_CH7OC)
5432 /*! @brief Set the CH7OC field to a new value. */
5433 #define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
5437 * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
5440 * - 0 - The software output control forces 0 to the channel output.
5441 * - 1 - The software output control forces 1 to the channel output.
5444 #define BP_FTM_SWOCTRL_CH0OCV (8U) /*!< Bit position for FTM_SWOCTRL_CH0OCV. */
5445 #define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) /*!< Bit mask for FTM_SWOCTRL_CH0OCV. */
5446 #define BS_FTM_SWOCTRL_CH0OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OCV. */
5448 /*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
5449 #define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
5451 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV. */
5452 #define BF_FTM_SWOCTRL_CH0OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OCV) & BM_FTM_SWOCTRL_CH0OCV)
5454 /*! @brief Set the CH0OCV field to a new value. */
5455 #define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
5459 * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
5462 * - 0 - The software output control forces 0 to the channel output.
5463 * - 1 - The software output control forces 1 to the channel output.
5466 #define BP_FTM_SWOCTRL_CH1OCV (9U) /*!< Bit position for FTM_SWOCTRL_CH1OCV. */
5467 #define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) /*!< Bit mask for FTM_SWOCTRL_CH1OCV. */
5468 #define BS_FTM_SWOCTRL_CH1OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OCV. */
5470 /*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
5471 #define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
5473 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV. */
5474 #define BF_FTM_SWOCTRL_CH1OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OCV) & BM_FTM_SWOCTRL_CH1OCV)
5476 /*! @brief Set the CH1OCV field to a new value. */
5477 #define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
5481 * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
5484 * - 0 - The software output control forces 0 to the channel output.
5485 * - 1 - The software output control forces 1 to the channel output.
5488 #define BP_FTM_SWOCTRL_CH2OCV (10U) /*!< Bit position for FTM_SWOCTRL_CH2OCV. */
5489 #define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) /*!< Bit mask for FTM_SWOCTRL_CH2OCV. */
5490 #define BS_FTM_SWOCTRL_CH2OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OCV. */
5492 /*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
5493 #define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
5495 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV. */
5496 #define BF_FTM_SWOCTRL_CH2OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OCV) & BM_FTM_SWOCTRL_CH2OCV)
5498 /*! @brief Set the CH2OCV field to a new value. */
5499 #define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
5503 * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
5506 * - 0 - The software output control forces 0 to the channel output.
5507 * - 1 - The software output control forces 1 to the channel output.
5510 #define BP_FTM_SWOCTRL_CH3OCV (11U) /*!< Bit position for FTM_SWOCTRL_CH3OCV. */
5511 #define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) /*!< Bit mask for FTM_SWOCTRL_CH3OCV. */
5512 #define BS_FTM_SWOCTRL_CH3OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OCV. */
5514 /*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
5515 #define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
5517 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV. */
5518 #define BF_FTM_SWOCTRL_CH3OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OCV) & BM_FTM_SWOCTRL_CH3OCV)
5520 /*! @brief Set the CH3OCV field to a new value. */
5521 #define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
5525 * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
5528 * - 0 - The software output control forces 0 to the channel output.
5529 * - 1 - The software output control forces 1 to the channel output.
5532 #define BP_FTM_SWOCTRL_CH4OCV (12U) /*!< Bit position for FTM_SWOCTRL_CH4OCV. */
5533 #define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) /*!< Bit mask for FTM_SWOCTRL_CH4OCV. */
5534 #define BS_FTM_SWOCTRL_CH4OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OCV. */
5536 /*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
5537 #define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
5539 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV. */
5540 #define BF_FTM_SWOCTRL_CH4OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OCV) & BM_FTM_SWOCTRL_CH4OCV)
5542 /*! @brief Set the CH4OCV field to a new value. */
5543 #define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
5547 * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
5550 * - 0 - The software output control forces 0 to the channel output.
5551 * - 1 - The software output control forces 1 to the channel output.
5554 #define BP_FTM_SWOCTRL_CH5OCV (13U) /*!< Bit position for FTM_SWOCTRL_CH5OCV. */
5555 #define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) /*!< Bit mask for FTM_SWOCTRL_CH5OCV. */
5556 #define BS_FTM_SWOCTRL_CH5OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OCV. */
5558 /*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
5559 #define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
5561 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV. */
5562 #define BF_FTM_SWOCTRL_CH5OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OCV) & BM_FTM_SWOCTRL_CH5OCV)
5564 /*! @brief Set the CH5OCV field to a new value. */
5565 #define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
5569 * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
5572 * - 0 - The software output control forces 0 to the channel output.
5573 * - 1 - The software output control forces 1 to the channel output.
5576 #define BP_FTM_SWOCTRL_CH6OCV (14U) /*!< Bit position for FTM_SWOCTRL_CH6OCV. */
5577 #define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) /*!< Bit mask for FTM_SWOCTRL_CH6OCV. */
5578 #define BS_FTM_SWOCTRL_CH6OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OCV. */
5580 /*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
5581 #define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
5583 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV. */
5584 #define BF_FTM_SWOCTRL_CH6OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OCV) & BM_FTM_SWOCTRL_CH6OCV)
5586 /*! @brief Set the CH6OCV field to a new value. */
5587 #define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
5591 * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
5594 * - 0 - The software output control forces 0 to the channel output.
5595 * - 1 - The software output control forces 1 to the channel output.
5598 #define BP_FTM_SWOCTRL_CH7OCV (15U) /*!< Bit position for FTM_SWOCTRL_CH7OCV. */
5599 #define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) /*!< Bit mask for FTM_SWOCTRL_CH7OCV. */
5600 #define BS_FTM_SWOCTRL_CH7OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OCV. */
5602 /*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
5603 #define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
5605 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV. */
5606 #define BF_FTM_SWOCTRL_CH7OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OCV) & BM_FTM_SWOCTRL_CH7OCV)
5608 /*! @brief Set the CH7OCV field to a new value. */
5609 #define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
5612 /*******************************************************************************
5613 * HW_FTM_PWMLOAD - FTM PWM Load
5614 ******************************************************************************/
5617 * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
5619 * Reset value: 0x00000000U
5621 * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
5622 * values of their write buffers when the FTM counter changes from the MOD
5623 * register value to its next value or when a channel (j) match occurs. A match occurs
5624 * for the channel (j) when FTM counter = C(j)V.
5626 typedef union _hw_ftm_pwmload
5629 struct _hw_ftm_pwmload_bitfields
5631 uint32_t CH0SEL : 1; /*!< [0] Channel 0 Select */
5632 uint32_t CH1SEL : 1; /*!< [1] Channel 1 Select */
5633 uint32_t CH2SEL : 1; /*!< [2] Channel 2 Select */
5634 uint32_t CH3SEL : 1; /*!< [3] Channel 3 Select */
5635 uint32_t CH4SEL : 1; /*!< [4] Channel 4 Select */
5636 uint32_t CH5SEL : 1; /*!< [5] Channel 5 Select */
5637 uint32_t CH6SEL : 1; /*!< [6] Channel 6 Select */
5638 uint32_t CH7SEL : 1; /*!< [7] Channel 7 Select */
5639 uint32_t RESERVED0 : 1; /*!< [8] */
5640 uint32_t LDOK : 1; /*!< [9] Load Enable */
5641 uint32_t RESERVED1 : 22; /*!< [31:10] */
5646 * @name Constants and macros for entire FTM_PWMLOAD register
5649 #define HW_FTM_PWMLOAD_ADDR(x) ((x) + 0x98U)
5651 #define HW_FTM_PWMLOAD(x) (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x))
5652 #define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U)
5653 #define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v))
5654 #define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) | (v)))
5655 #define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
5656 #define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v)))
5660 * Constants & macros for individual FTM_PWMLOAD bitfields
5664 * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
5667 * - 0 - Do not include the channel in the matching process.
5668 * - 1 - Include the channel in the matching process.
5671 #define BP_FTM_PWMLOAD_CH0SEL (0U) /*!< Bit position for FTM_PWMLOAD_CH0SEL. */
5672 #define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) /*!< Bit mask for FTM_PWMLOAD_CH0SEL. */
5673 #define BS_FTM_PWMLOAD_CH0SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH0SEL. */
5675 /*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
5676 #define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
5678 /*! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL. */
5679 #define BF_FTM_PWMLOAD_CH0SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH0SEL) & BM_FTM_PWMLOAD_CH0SEL)
5681 /*! @brief Set the CH0SEL field to a new value. */
5682 #define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
5686 * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
5689 * - 0 - Do not include the channel in the matching process.
5690 * - 1 - Include the channel in the matching process.
5693 #define BP_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit position for FTM_PWMLOAD_CH1SEL. */
5694 #define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) /*!< Bit mask for FTM_PWMLOAD_CH1SEL. */
5695 #define BS_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH1SEL. */
5697 /*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
5698 #define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
5700 /*! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL. */
5701 #define BF_FTM_PWMLOAD_CH1SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH1SEL) & BM_FTM_PWMLOAD_CH1SEL)
5703 /*! @brief Set the CH1SEL field to a new value. */
5704 #define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
5708 * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
5711 * - 0 - Do not include the channel in the matching process.
5712 * - 1 - Include the channel in the matching process.
5715 #define BP_FTM_PWMLOAD_CH2SEL (2U) /*!< Bit position for FTM_PWMLOAD_CH2SEL. */
5716 #define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) /*!< Bit mask for FTM_PWMLOAD_CH2SEL. */
5717 #define BS_FTM_PWMLOAD_CH2SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH2SEL. */
5719 /*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
5720 #define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
5722 /*! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL. */
5723 #define BF_FTM_PWMLOAD_CH2SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH2SEL) & BM_FTM_PWMLOAD_CH2SEL)
5725 /*! @brief Set the CH2SEL field to a new value. */
5726 #define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
5730 * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
5733 * - 0 - Do not include the channel in the matching process.
5734 * - 1 - Include the channel in the matching process.
5737 #define BP_FTM_PWMLOAD_CH3SEL (3U) /*!< Bit position for FTM_PWMLOAD_CH3SEL. */
5738 #define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) /*!< Bit mask for FTM_PWMLOAD_CH3SEL. */
5739 #define BS_FTM_PWMLOAD_CH3SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH3SEL. */
5741 /*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
5742 #define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
5744 /*! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL. */
5745 #define BF_FTM_PWMLOAD_CH3SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH3SEL) & BM_FTM_PWMLOAD_CH3SEL)
5747 /*! @brief Set the CH3SEL field to a new value. */
5748 #define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
5752 * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
5755 * - 0 - Do not include the channel in the matching process.
5756 * - 1 - Include the channel in the matching process.
5759 #define BP_FTM_PWMLOAD_CH4SEL (4U) /*!< Bit position for FTM_PWMLOAD_CH4SEL. */
5760 #define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) /*!< Bit mask for FTM_PWMLOAD_CH4SEL. */
5761 #define BS_FTM_PWMLOAD_CH4SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH4SEL. */
5763 /*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
5764 #define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
5766 /*! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL. */
5767 #define BF_FTM_PWMLOAD_CH4SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH4SEL) & BM_FTM_PWMLOAD_CH4SEL)
5769 /*! @brief Set the CH4SEL field to a new value. */
5770 #define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
5774 * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
5777 * - 0 - Do not include the channel in the matching process.
5778 * - 1 - Include the channel in the matching process.
5781 #define BP_FTM_PWMLOAD_CH5SEL (5U) /*!< Bit position for FTM_PWMLOAD_CH5SEL. */
5782 #define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) /*!< Bit mask for FTM_PWMLOAD_CH5SEL. */
5783 #define BS_FTM_PWMLOAD_CH5SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH5SEL. */
5785 /*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
5786 #define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
5788 /*! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL. */
5789 #define BF_FTM_PWMLOAD_CH5SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH5SEL) & BM_FTM_PWMLOAD_CH5SEL)
5791 /*! @brief Set the CH5SEL field to a new value. */
5792 #define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
5796 * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
5799 * - 0 - Do not include the channel in the matching process.
5800 * - 1 - Include the channel in the matching process.
5803 #define BP_FTM_PWMLOAD_CH6SEL (6U) /*!< Bit position for FTM_PWMLOAD_CH6SEL. */
5804 #define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) /*!< Bit mask for FTM_PWMLOAD_CH6SEL. */
5805 #define BS_FTM_PWMLOAD_CH6SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH6SEL. */
5807 /*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
5808 #define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
5810 /*! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL. */
5811 #define BF_FTM_PWMLOAD_CH6SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH6SEL) & BM_FTM_PWMLOAD_CH6SEL)
5813 /*! @brief Set the CH6SEL field to a new value. */
5814 #define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
5818 * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
5821 * - 0 - Do not include the channel in the matching process.
5822 * - 1 - Include the channel in the matching process.
5825 #define BP_FTM_PWMLOAD_CH7SEL (7U) /*!< Bit position for FTM_PWMLOAD_CH7SEL. */
5826 #define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) /*!< Bit mask for FTM_PWMLOAD_CH7SEL. */
5827 #define BS_FTM_PWMLOAD_CH7SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH7SEL. */
5829 /*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
5830 #define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
5832 /*! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL. */
5833 #define BF_FTM_PWMLOAD_CH7SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH7SEL) & BM_FTM_PWMLOAD_CH7SEL)
5835 /*! @brief Set the CH7SEL field to a new value. */
5836 #define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
5840 * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
5842 * Enables the loading of the MOD, CNTIN, and CV registers with the values of
5843 * their write buffers.
5846 * - 0 - Loading updated values is disabled.
5847 * - 1 - Loading updated values is enabled.
5850 #define BP_FTM_PWMLOAD_LDOK (9U) /*!< Bit position for FTM_PWMLOAD_LDOK. */
5851 #define BM_FTM_PWMLOAD_LDOK (0x00000200U) /*!< Bit mask for FTM_PWMLOAD_LDOK. */
5852 #define BS_FTM_PWMLOAD_LDOK (1U) /*!< Bit field size in bits for FTM_PWMLOAD_LDOK. */
5854 /*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
5855 #define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
5857 /*! @brief Format value for bitfield FTM_PWMLOAD_LDOK. */
5858 #define BF_FTM_PWMLOAD_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_LDOK) & BM_FTM_PWMLOAD_LDOK)
5860 /*! @brief Set the LDOK field to a new value. */
5861 #define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
5864 /*******************************************************************************
5865 * hw_ftm_t - module struct
5866 ******************************************************************************/
5868 * @brief All FTM module registers.
5871 typedef struct _hw_ftm
5873 __IO hw_ftm_sc_t SC; /*!< [0x0] Status And Control */
5874 __IO hw_ftm_cnt_t CNT; /*!< [0x4] Counter */
5875 __IO hw_ftm_mod_t MOD; /*!< [0x8] Modulo */
5877 __IO hw_ftm_cnsc_t CnSC; /*!< [0xC] Channel (n) Status And Control */
5878 __IO hw_ftm_cnv_t CnV; /*!< [0x10] Channel (n) Value */
5880 __IO hw_ftm_cntin_t CNTIN; /*!< [0x4C] Counter Initial Value */
5881 __IO hw_ftm_status_t STATUS; /*!< [0x50] Capture And Compare Status */
5882 __IO hw_ftm_mode_t MODE; /*!< [0x54] Features Mode Selection */
5883 __IO hw_ftm_sync_t SYNC; /*!< [0x58] Synchronization */
5884 __IO hw_ftm_outinit_t OUTINIT; /*!< [0x5C] Initial State For Channels Output */
5885 __IO hw_ftm_outmask_t OUTMASK; /*!< [0x60] Output Mask */
5886 __IO hw_ftm_combine_t COMBINE; /*!< [0x64] Function For Linked Channels */
5887 __IO hw_ftm_deadtime_t DEADTIME; /*!< [0x68] Deadtime Insertion Control */
5888 __IO hw_ftm_exttrig_t EXTTRIG; /*!< [0x6C] FTM External Trigger */
5889 __IO hw_ftm_pol_t POL; /*!< [0x70] Channels Polarity */
5890 __IO hw_ftm_fms_t FMS; /*!< [0x74] Fault Mode Status */
5891 __IO hw_ftm_filter_t FILTER; /*!< [0x78] Input Capture Filter Control */
5892 __IO hw_ftm_fltctrl_t FLTCTRL; /*!< [0x7C] Fault Control */
5893 __IO hw_ftm_qdctrl_t QDCTRL; /*!< [0x80] Quadrature Decoder Control And Status */
5894 __IO hw_ftm_conf_t CONF; /*!< [0x84] Configuration */
5895 __IO hw_ftm_fltpol_t FLTPOL; /*!< [0x88] FTM Fault Input Polarity */
5896 __IO hw_ftm_synconf_t SYNCONF; /*!< [0x8C] Synchronization Configuration */
5897 __IO hw_ftm_invctrl_t INVCTRL; /*!< [0x90] FTM Inverting Control */
5898 __IO hw_ftm_swoctrl_t SWOCTRL; /*!< [0x94] FTM Software Output Control */
5899 __IO hw_ftm_pwmload_t PWMLOAD; /*!< [0x98] FTM PWM Load */
5903 /*! @brief Macro to access all FTM registers. */
5904 /*! @param x FTM module instance base address. */
5905 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
5906 * use the '&' operator, like <code>&HW_FTM(FTM0_BASE)</code>. */
5907 #define HW_FTM(x) (*(hw_ftm_t *)(x))
5909 #endif /* __HW_FTM_REGISTERS_H__ */