+#define XT_RST_PORT PORTB
+#define XT_RST_PIN PINB
+#define XT_RST_DDR DDRB
+#define XT_RST_BIT 7
+
+/* hard reset: low pulse for 500ms and after that HiZ for safety */
+#define XT_RESET() do { \
+ XT_RST_PORT &= ~(1<<XT_RST_BIT); \
+ XT_RST_DDR |= (1<<XT_RST_BIT); \
+ _delay_ms(500); \
+ XT_RST_DDR &= ~(1<<XT_RST_BIT); \
+} while (0)
+
+/* INT1 for falling edge of clock line */