+// Matrix I/O ports
+//
+// row: HC4051[A,B,C] selects scan row0-7
+// col: LS145[A,B,C,D] selects scan col0-7 and enable(D)
+// key: on: 0/off: 1
+// prev: unknown: output previous key state(negated)?
+
+#ifdef HOST_PJRC
+// Ports for Teensy
+// row: PB0-2
+// col: PB3-5,6
+// key: PE6(pull-uped)
+// prev: PE7
+#define KEY_INIT() do { \
+ DDRB |= 0x7F; \
+ DDRE |= (1<<7); \
+ DDRE &= ~(1<<6); \
+ PORTE |= (1<<6); \
+} while (0)
+#define KEY_SELECT(ROW, COL) (PORTB = (PORTB & 0xC0) | \
+ (((COL) & 0x07)<<3) | \
+ ((ROW) & 0x07))
+#define KEY_ENABLE() (PORTB &= ~(1<<6))
+#define KEY_UNABLE() (PORTB |= (1<<6))
+#define KEY_STATE() (PINE & (1<<6))
+#define KEY_PREV_ON() (PORTE |= (1<<7))
+#define KEY_PREV_OFF() (PORTE &= ~(1<<7))
+
+#else
+// Ports for V-USB
+// key: PB0(pull-uped)
+// prev: PB1
+// row: PB2-4
+// col: PC0-2,3
+#define KEY_INIT() do { \
+ DDRB |= 0x1E; \
+ DDRB &= ~(1<<0); \
+ PORTB |= (1<<0); \
+ DDRC |= 0x0F; \
+} while (0)
+#define KEY_SELECT(ROW, COL) do { \
+ PORTB = (PORTB & 0xE3) | ((ROW) & 0x07)<<2; \
+ PORTC = (PORTC & 0xF8) | ((COL) & 0x07); \
+} while (0)
+#define KEY_ENABLE() (PORTC &= ~(1<<3))
+#define KEY_UNABLE() (PORTC |= (1<<3))
+#define KEY_STATE() (PINB & (1<<0))
+#define KEY_PREV_ON() (PORTB |= (1<<1))
+#define KEY_PREV_OFF() (PORTB &= ~(1<<1))
+#endif