--- /dev/null
+# Target file name (without extension).
+PROJECT = kl27z_kbd
+
+# Directory common source files exist
+TMK_DIR = ../../tmk_core
+
+# Directory keyboard dependent files exist
+TARGET_DIR = .
+
+# project specific files
+SRC = $(PROJECT).c
+
+CONFIG_H = config.h
+
+## chip/board settings
+# - the next two should match the directories in
+# <chibios>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
+# - For Teensies, FAMILY = KINETIS and SERIES is either
+# KL2x (LC) or K20x (3.0,3.1,3.2).
+MCU_FAMILY = KINETIS
+MCU_SERIES = KL2x
+
+# Linker script to use
+# - it should exist either in <chibios>/os/common/ports/ARMCMx/compilers/GCC/ld/
+# or <this_dir>/ld/
+# - NOTE: a custom ld script is needed for EEPROM on Teensy LC
+# - LDSCRIPT =
+# - MKL26Z64 for Teensy LC
+# - MK20DX128 for Teensy 3.0
+# - MK20DX256 for Teensy 3.1 and 3.2
+MCU_LDSCRIPT = MKL27Z256
+
+# Startup code to use
+# - it should exist in <chibios>/os/common/ports/ARMCMx/compilers/GCC/mk/
+# - STARTUP =
+# - kl2x for Teensy LC
+# - k20x5 for Teensy 3.0
+# - k20x7 for Teensy 3.1 and 3.2
+MCU_STARTUP = kl2x
+
+# Board: it should exist either in <chibios>/os/hal/boards/
+# or <this_dir>/boards
+# - BOARD =
+# - PJRC_TEENSY_LC for Teensy LC
+# - PJRC_TEENSY_3 for Teensy 3.0
+# - PJRC_TEENSY_3_1 for Teensy 3.1 or 3.2
+BOARD = ELF
+
+# Cortex version
+# Teensy LC is cortex-m0plus; Teensy 3.x are cortex-m4
+MCU = cortex-m0plus
+
+# ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
+# I.e. 6 for Teensy LC; 7 for Teensy 3.x
+ARMV = 6
+
+# Build Options
+# comment out to disable the options.
+#
+#BOOTMAGIC_ENABLE = yes # Virtual DIP switch configuration
+## (Note that for BOOTMAGIC on Teensy LC you have to use a custom .ld script.)
+#MOUSEKEY_ENABLE = yes # Mouse keys
+EXTRAKEY_ENABLE = yes # Audio control and System control
+CONSOLE_ENABLE = yes # Console for debug
+#COMMAND_ENABLE = yes # Commands for debug and configuration
+#SLEEP_LED_ENABLE = yes # Breathing sleep LED during USB suspend
+#NKRO_ENABLE = yes # USB Nkey Rollover
+
+include $(TMK_DIR)/tool/chibios/common.mk
+include $(TMK_DIR)/tool/chibios/chibios.mk
--- /dev/null
+COL
+---
+Anode side, senses keys with internal pull-up.
+
+Left to right:
+
+ PTD6
+ PTD5
+ PTD4
+ PTD3
+
+ PTA19
+ PTA18
+ PTA4 NMI
+ PTA2
+ PTA1
+
+ PTE25
+ PTE24
+ PTE30
+ PTE29
+ PTE21
+
+ROW
+----
+Cathod side, given strobe with output low.
+
+Top to bottom:
+
+ PTB3
+ PTB16
+ PTB17
+ PTC0
+ PTC1
--- /dev/null
+KL27Z128/256 board
+==================
+2016/11/30
+
+KL27Z is configured to use internal 48MHz RC oscillator.
+
+The board has push button on PTA4 and LED on PTD7. The button works as 'a' key and the LED as an indicator for capslock.
+
+
+ELF board
+---------
+This board acommodates 48QFN chip.
+
+### prototypte pinout
+- pcb layout https://deskthority.net/resources/image/33293
+- schematic https://deskthority.net/resources/image/33252
+
+
+```
+ G G
+ N 5 D D N F D D D D D D
+ D V - + D G \ USB / 6 5 4 3 2 1
+ ,--------------------- | Conn | --------------------.
+ |39 40 41 42 43 44 | | 1 2 3 4 5 6 |
+ 3.3V|38 |_________| 7 |D0
+ A0|37 RST 8 |C7
+ A3|36 9 |C6
+ +A20|35 10|C5+
+ E20|34 11|C4
+ E21|33 BL 12|C3
+ E29|32 13|C2
+ |31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14|
+ `-------------------------------------------------------'
+ E E E A A A 3 A G A C B B B B B C C
+ 3 2 2 1 2 4 . 1 N 1 1 1 2 3 1 1 0 1
+ 0 4 5 + + 3V 8 D 9 6 7
+
+
+ 1 PTD6 12 PTC3 23 GND 34 PTE20*
+ 2 PTD5 13 PTC2 24 PTA18 35 PTA20/Reset+
+ 3 PTD4 14 PTC1 25 3.3V 36 PTA3/SWD_DIO
+ 4 PTD3* 15 PTC0* 26 PTA4/NMI+ 37 PTA0/SWD_CLK
+ 5 PTD2* 16 PTB17* 27 PTA2 38 3.3V
+ 6 PTD1* 17 PTB16* 28 PTA1+ 39 GND
+ 7 PTD0* 18 PTB3* 29 PTE25* 40 VBUS/VREGIN/5V
+ 8 PTC7 19 PTB2* 30 PTE24* 41 USB D-
+ 9 PTC6 20 PTB1 31 PTE30 42 USB D+
+ 10 PTC5+ 21 PTB0 32 PTE29* 43 GND
+ 11 PTC4 22 PTA19 33 PTE21* 44 USB Shield/FB
+ +: Pins with resistor or switch
+ *: Pins which don't exist in QFN32
+```
+
+
+TMK KL27Z breakout
+------------------
+This board acommodates 48QFN chip.
+
+### Pinputs
+
+ _\ conn /_
+ 1 28
+ : :
+ : PROG :
+ : RST :
+ 14 15
+ ----------
+
+ 1 VUSB 28 GND
+ 2 VIN/VREGIN 27 PTD4
+ 3 PTD5 26 PTC7
+ 4 PTD6 25 PTC6
+ 5 PTD7 24 PTC5+
+ 6 PTE0* 23 PTC4
+
+ 7 3.3V 22 GND
+ 8 PTE30 21 PTC3
+ 9 PTA0/SWD_CLK 20 PTC2
+ 10 PTA1+ 19 PTC1
+ 11 PTA2 18 PTB1
+ 12 PTA3/SWD_DIO 17 PTB0
+ 13 PTA4/NMI+ 16 PTA20/Reset+
+ 14 PTA18 15 PTA19
+ *: Pin which doesn't exist in QFN48
+
+
+#### Pinouts difference between 32QFN and 48QFN
+48QFN doesn't have PTE0
+32QFN doesn't have PTD0-3, PTC0, PTE20-21,24,25,29, PTB2-3,16,17
+
+### ROM bootloader pins
+See Reference Manual Chapter 13.
+
+ PTA2 LPUART0_TX
+ PTA1 LPUART0_RX *
+ PTB0 I2C0_SCL
+ PTB1 I2C0_SDA
+ PTC4 SPI0_SS_b *
+ PTC7 SPI0_MISO
+ PTC6 SPI0_MOSI
+ PTC5 SPI0_SCK *
+
+Due to errata e9457, need to pull-up `SPI0_SS_b`(or `SPI0_SCK`) to prevent false detection of SPI.
+The errata doesn't refer UART though, `LPUART0_RX` also requires pull-up or down resisitor from experience.
+Without resistor it easily false-detects activity on UART interface with finger touch on the pin.
+
+
+
+
+Resources
+---------
+### Deskthority thread
+https://deskthority.net/workshop-f7/can-we-design-the-teensy-alternative-for-keyboards-t13662-510.html
+
+### Kinetis KL2x
+http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/kinetis-cortex-m-mcus/l-series-ultra-low-power-m0-plus/kinetis-kl2x-48-mhz-usb-ultra-low-power-microcontrollers-based-on-arm-cortex-m0-plus:KL2x
+
+### KL27Z128/256 Data Sheet
+http://www.nxp.com/assets/documents/data/en/data-sheets/KL27P64M48SF6.pdf
+
+### KL27Z128/256 Reference Manual
+http://www.nxp.com/assets/documents/data/en/reference-manuals/KL27P64M48SF6RM.pdf
+
+### Errata
+http://www.nxp.com/assets/documents/data/en/errata/KINETIS_L_1N71K.pdf
+
+>>
+e9457: Kinetis Flashloader/ ROM Bootloader: The peripheral auto-detect code in
+bootloader can falsely detect presence of SPI host causing non-responsive
+bootloader
+Description: During the active peripheral detection process, the bootloader can interpret spurious data on
+the SPI peripheral as valid data. The spurious data causes the bootloader to shutdown all
+peripherals except the “falsely detected" SPI and enter the command phase loop using the
+SPI. After the bootloader enters the command phase loop using the SPI, the other peripherals
+are ignored, so the desired peripheral is no longer active.
+The bootloader will not falsely detect activity on the I2C, UART, or USB interfaces, so only the
+SPI interface is affected.
+Workaround: Ensure that there is an external pull-up on the SPI chip-select pin or that the pin is driven high.
+This will prevent the bootloader from seeing spurious data due to activity on the SPI clock pin.
+
+### Kinetis Bootloader and blhost
+http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/kinetis-cortex-m-mcus/kinetis-symbols-footprints-and-models/kinetis-bootloader:KBOOT
+
+
+Build
+-----
+
+ make
+
+
+Program
+-------
+Flash firmware with ROM bootloader.
+
+ blhost -u -- flash-image build/kl27z.hex erase
+
+
+TODO
+----
+- Fix boards/ELF files
+- add macro `USBx_CTL_RESUME` to ChibiOS-Contrib/os/common/ext/CMSIS/KINETIS/kl27zxxx.h
--- /dev/null
+/*\r
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+#include "ch.h"\r
+#include "hal.h"\r
+\r
+#if HAL_USE_PAL || defined(__DOXYGEN__)\r
+/**\r
+ * @brief PAL setup.\r
+ * @details Digital I/O ports static configuration as defined in @p board.h.\r
+ * This variable is used by the HAL when initializing the PAL driver.\r
+ */\r
+const PALConfig pal_default_config =\r
+{\r
+ .ports = {\r
+ {\r
+ /*\r
+ * PORTA setup.\r
+ *\r
+ * on pads: PTA1, PTA2, PTA5, PTA18, PTA19\r
+ *\r
+ * PTA0/3 SWD (default SWD, ALT_7: SWD, ALT_1: PTA0/3)\r
+ * PTA4 NMI button (default NMI_b, ALT_1: PTA4)\r
+ * PTA20 RESET button (default RESET, ALT_7: RESET, ALT_1: PTA20)\r
+ */\r
+ .port = IOPORT1,\r
+ .pads = {\r
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_INPUT_PULLUP, PAL_MODE_OUTPUT_PUSHPULL,\r
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_ALTERNATIVE_7,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ },\r
+ },\r
+ {\r
+ /*\r
+ * PORTB setup.\r
+ *\r
+ * on pads: PTB0, PTB1\r
+ * LED: PTB18\r
+ */\r
+ .port = IOPORT2,\r
+ .pads = {\r
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ },\r
+ },\r
+ {\r
+ /*\r
+ * PORTC setup.\r
+ *\r
+ * on pads: PTC1, PTC2, PTC3, PTC6, PTC7, PTC8, PTC9\r
+ */\r
+ .port = IOPORT3,\r
+ .pads = {\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,\r
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,\r
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ },\r
+ },\r
+ {\r
+ /*\r
+ * PORTD setup.\r
+ *\r
+ * on pads: PTD0 - PTD7\r
+ */\r
+ .port = IOPORT4,\r
+ .pads = {\r
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,\r
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,\r
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ },\r
+ },\r
+ {\r
+ /*\r
+ * PORTE setup.\r
+ *\r
+ * on pads: PTE0, PTE1, PTE24, PTE25, PTE29, PTE30\r
+ */\r
+ .port = IOPORT5,\r
+ .pads = {\r
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED,\r
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_INPUT_PULLUP,\r
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED,\r
+ },\r
+ },\r
+ },\r
+};\r
+#endif\r
+\r
+/**\r
+ * @brief Early initialization code.\r
+ * @details This initialization must be performed just after stack setup\r
+ * and before any other initialization.\r
+ */\r
+void __early_init(void) {\r
+\r
+ kl2x_clock_init();\r
+}\r
+\r
+/**\r
+ * @brief Board-specific initialization code.\r
+ * @todo Add your board-specific code, if any.\r
+ */\r
+void boardInit(void) {\r
+}\r
--- /dev/null
+/*\r
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+/*\r
+ * Setup for a custom KL27Z breakout board.\r
+ */\r
+\r
+/*\r
+ * Board identifier.\r
+ */\r
+#define BOARD_KL27Z_BREAKOUT\r
+#define BOARD_NAME "Custom KL27Z breakout"\r
+\r
+/*\r
+ * MCU type\r
+ */\r
+#define KL27Zxxx\r
+\r
+/*\r
+ * Onboard features.\r
+ */\r
+//#define GPIO_LED IOPORT1\r
+//#define PIN_LED 2\r
+// PTD7 on ELF\r
+#define GPIO_LED IOPORT4\r
+#define PIN_LED 7\r
+#define GPIO_BUTTON IOPORT1\r
+#define PIN_BUTTON 4\r
+\r
+#if !defined(_FROM_ASM_)\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+ void boardInit(void);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* _FROM_ASM_ */\r
+\r
+#endif /* _BOARD_H_ */\r
--- /dev/null
+# List of all the board related files.\r
+BOARDSRC = ./boards/ELF/board.c\r
+\r
+# Required include directories\r
+BOARDINC = ./boards/ELF\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/**\r
+ * @file templates/chconf.h\r
+ * @brief Configuration file template.\r
+ * @details A copy of this file must be placed in each project directory, it\r
+ * contains the application specific kernel settings.\r
+ *\r
+ * @addtogroup config\r
+ * @details Kernel related settings and hooks.\r
+ * @{\r
+ */\r
+\r
+#ifndef CHCONF_H\r
+#define CHCONF_H\r
+\r
+#define _CHIBIOS_RT_CONF_\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name System timers settings\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief System time counter resolution.\r
+ * @note Allowed values are 16 or 32 bits.\r
+ */\r
+#define CH_CFG_ST_RESOLUTION 32\r
+\r
+/**\r
+ * @brief System tick frequency.\r
+ * @details Frequency of the system timer that drives the system ticks. This\r
+ * setting also defines the system tick time unit.\r
+ */\r
+#define CH_CFG_ST_FREQUENCY 1000\r
+\r
+/**\r
+ * @brief Time delta constant for the tick-less mode.\r
+ * @note If this value is zero then the system uses the classic\r
+ * periodic tick. This value represents the minimum number\r
+ * of ticks that is safe to specify in a timeout directive.\r
+ * The value one is not valid, timeouts are rounded up to\r
+ * this value.\r
+ */\r
+#define CH_CFG_ST_TIMEDELTA 0\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Kernel parameters and options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Round robin interval.\r
+ * @details This constant is the number of system ticks allowed for the\r
+ * threads before preemption occurs. Setting this value to zero\r
+ * disables the preemption for threads with equal priority and the\r
+ * round robin becomes cooperative. Note that higher priority\r
+ * threads can still preempt, the kernel is always preemptive.\r
+ * @note Disabling the round robin preemption makes the kernel more compact\r
+ * and generally faster.\r
+ * @note The round robin preemption is not supported in tickless mode and\r
+ * must be set to zero in that case.\r
+ */\r
+#define CH_CFG_TIME_QUANTUM 20\r
+\r
+/**\r
+ * @brief Managed RAM size.\r
+ * @details Size of the RAM area to be managed by the OS. If set to zero\r
+ * then the whole available RAM is used. The core memory is made\r
+ * available to the heap allocator and/or can be used directly through\r
+ * the simplified core memory allocator.\r
+ *\r
+ * @note In order to let the OS manage the whole RAM the linker script must\r
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.\r
+ * @note Requires @p CH_CFG_USE_MEMCORE.\r
+ */\r
+#define CH_CFG_MEMCORE_SIZE 0\r
+\r
+/**\r
+ * @brief Idle thread automatic spawn suppression.\r
+ * @details When this option is activated the function @p chSysInit()\r
+ * does not spawn the idle thread. The application @p main()\r
+ * function becomes the idle thread and must implement an\r
+ * infinite loop.\r
+ */\r
+#define CH_CFG_NO_IDLE_THREAD FALSE\r
+\r
+/* Use __WFI in the idle thread for waiting. Does lower the power\r
+ * consumption. */\r
+#define CORTEX_ENABLE_WFI_IDLE TRUE\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Performance options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief OS optimization.\r
+ * @details If enabled then time efficient rather than space efficient code\r
+ * is used when two possible implementations exist.\r
+ *\r
+ * @note This is not related to the compiler optimization options.\r
+ * @note The default is @p TRUE.\r
+ */\r
+#define CH_CFG_OPTIMIZE_SPEED TRUE\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Subsystem options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Time Measurement APIs.\r
+ * @details If enabled then the time measurement APIs are included in\r
+ * the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#define CH_CFG_USE_TM FALSE\r
+\r
+/**\r
+ * @brief Threads registry APIs.\r
+ * @details If enabled then the registry APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#define CH_CFG_USE_REGISTRY TRUE\r
+\r
+/**\r
+ * @brief Threads synchronization APIs.\r
+ * @details If enabled then the @p chThdWait() function is included in\r
+ * the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#define CH_CFG_USE_WAITEXIT TRUE\r
+\r
+/**\r
+ * @brief Semaphores APIs.\r
+ * @details If enabled then the Semaphores APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#define CH_CFG_USE_SEMAPHORES TRUE\r
+\r
+/**\r
+ * @brief Semaphores queuing mode.\r
+ * @details If enabled then the threads are enqueued on semaphores by\r
+ * priority rather than in FIFO order.\r
+ *\r
+ * @note The default is @p FALSE. Enable this if you have special\r
+ * requirements.\r
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.\r
+ */\r
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE\r
+\r
+/**\r
+ * @brief Mutexes APIs.\r
+ * @details If enabled then the mutexes APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#define CH_CFG_USE_MUTEXES TRUE\r
+\r
+/**\r
+ * @brief Enables recursive behavior on mutexes.\r
+ * @note Recursive mutexes are heavier and have an increased\r
+ * memory footprint.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note Requires @p CH_CFG_USE_MUTEXES.\r
+ */\r
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE\r
+\r
+/**\r
+ * @brief Conditional Variables APIs.\r
+ * @details If enabled then the conditional variables APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_MUTEXES.\r
+ */\r
+#define CH_CFG_USE_CONDVARS TRUE\r
+\r
+/**\r
+ * @brief Conditional Variables APIs with timeout.\r
+ * @details If enabled then the conditional variables APIs with timeout\r
+ * specification are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_CONDVARS.\r
+ */\r
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE\r
+\r
+/**\r
+ * @brief Events Flags APIs.\r
+ * @details If enabled then the event flags APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#define CH_CFG_USE_EVENTS TRUE\r
+\r
+/**\r
+ * @brief Events Flags APIs with timeout.\r
+ * @details If enabled then the events APIs with timeout specification\r
+ * are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_EVENTS.\r
+ */\r
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE\r
+\r
+/**\r
+ * @brief Synchronous Messages APIs.\r
+ * @details If enabled then the synchronous messages APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#define CH_CFG_USE_MESSAGES TRUE\r
+\r
+/**\r
+ * @brief Synchronous Messages queuing mode.\r
+ * @details If enabled then messages are served by priority rather than in\r
+ * FIFO order.\r
+ *\r
+ * @note The default is @p FALSE. Enable this if you have special\r
+ * requirements.\r
+ * @note Requires @p CH_CFG_USE_MESSAGES.\r
+ */\r
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE\r
+\r
+/**\r
+ * @brief Mailboxes APIs.\r
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are\r
+ * included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.\r
+ */\r
+#define CH_CFG_USE_MAILBOXES TRUE\r
+\r
+/**\r
+ * @brief Core Memory Manager APIs.\r
+ * @details If enabled then the core memory manager APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#define CH_CFG_USE_MEMCORE TRUE\r
+\r
+/**\r
+ * @brief Heap Allocator APIs.\r
+ * @details If enabled then the memory heap allocator APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or\r
+ * @p CH_CFG_USE_SEMAPHORES.\r
+ * @note Mutexes are recommended.\r
+ */\r
+#define CH_CFG_USE_HEAP TRUE\r
+\r
+/**\r
+ * @brief Memory Pools Allocator APIs.\r
+ * @details If enabled then the memory pools allocator APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#define CH_CFG_USE_MEMPOOLS TRUE\r
+\r
+/**\r
+ * @brief Dynamic Threads APIs.\r
+ * @details If enabled then the dynamic threads creation APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_WAITEXIT.\r
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.\r
+ */\r
+#define CH_CFG_USE_DYNAMIC TRUE\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Debug options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Debug option, kernel statistics.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#define CH_DBG_STATISTICS FALSE\r
+\r
+/**\r
+ * @brief Debug option, system state check.\r
+ * @details If enabled the correct call protocol for system APIs is checked\r
+ * at runtime.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE\r
+\r
+/**\r
+ * @brief Debug option, parameters checks.\r
+ * @details If enabled then the checks on the API functions input\r
+ * parameters are activated.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#define CH_DBG_ENABLE_CHECKS TRUE\r
+\r
+/**\r
+ * @brief Debug option, consistency checks.\r
+ * @details If enabled then all the assertions in the kernel code are\r
+ * activated. This includes consistency checks inside the kernel,\r
+ * runtime anomalies and port-defined checks.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#define CH_DBG_ENABLE_ASSERTS TRUE\r
+\r
+/**\r
+ * @brief Debug option, trace buffer.\r
+ * @details If enabled then the trace buffer is activated.\r
+ *\r
+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.\r
+ */\r
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED\r
+\r
+/**\r
+ * @brief Trace buffer entries.\r
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is\r
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.\r
+ */\r
+#define CH_DBG_TRACE_BUFFER_SIZE 128\r
+\r
+/**\r
+ * @brief Debug option, stack checks.\r
+ * @details If enabled then a runtime stack check is performed.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note The stack check is performed in a architecture/port dependent way.\r
+ * It may not be implemented or some ports.\r
+ * @note The default failure mode is to halt the system with the global\r
+ * @p panic_msg variable set to @p NULL.\r
+ */\r
+#define CH_DBG_ENABLE_STACK_CHECK TRUE\r
+\r
+/**\r
+ * @brief Debug option, stacks initialization.\r
+ * @details If enabled then the threads working area is filled with a byte\r
+ * value when a thread is created. This can be useful for the\r
+ * runtime measurement of the used stack.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#define CH_DBG_FILL_THREADS TRUE\r
+\r
+/**\r
+ * @brief Debug option, threads profiling.\r
+ * @details If enabled then a field is added to the @p thread_t structure that\r
+ * counts the system ticks occurred while executing the thread.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note This debug option is not currently compatible with the\r
+ * tickless mode.\r
+ */\r
+#define CH_DBG_THREADS_PROFILING FALSE\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Kernel hooks\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Threads descriptor structure extension.\r
+ * @details User fields added to the end of the @p thread_t structure.\r
+ */\r
+#define CH_CFG_THREAD_EXTRA_FIELDS \\r
+ /* Add threads custom fields here.*/\r
+\r
+/**\r
+ * @brief Threads initialization hook.\r
+ * @details User initialization code added to the @p chThdInit() API.\r
+ *\r
+ * @note It is invoked from within @p chThdInit() and implicitly from all\r
+ * the threads creation APIs.\r
+ */\r
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \\r
+ /* Add threads initialization code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Threads finalization hook.\r
+ * @details User finalization code added to the @p chThdExit() API.\r
+ */\r
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \\r
+ /* Add threads finalization code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Context switch hook.\r
+ * @details This hook is invoked just before switching between threads.\r
+ */\r
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \\r
+ /* Context switch code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief ISR enter hook.\r
+ */\r
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \\r
+ /* IRQ prologue code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief ISR exit hook.\r
+ */\r
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \\r
+ /* IRQ epilogue code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Idle thread enter hook.\r
+ * @note This hook is invoked within a critical zone, no OS functions\r
+ * should be invoked from here.\r
+ * @note This macro can be used to activate a power saving mode.\r
+ */\r
+#define CH_CFG_IDLE_ENTER_HOOK() { \\r
+ /* Idle-enter code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Idle thread leave hook.\r
+ * @note This hook is invoked within a critical zone, no OS functions\r
+ * should be invoked from here.\r
+ * @note This macro can be used to deactivate a power saving mode.\r
+ */\r
+#define CH_CFG_IDLE_LEAVE_HOOK() { \\r
+ /* Idle-leave code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Idle Loop hook.\r
+ * @details This hook is continuously invoked by the idle thread loop.\r
+ */\r
+#define CH_CFG_IDLE_LOOP_HOOK() { \\r
+ /* Idle loop code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief System tick event hook.\r
+ * @details This hook is invoked in the system tick handler immediately\r
+ * after processing the virtual timers queue.\r
+ */\r
+#define CH_CFG_SYSTEM_TICK_HOOK() { \\r
+ /* System tick event code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief System halt hook.\r
+ * @details This hook is invoked in case to a system halting error before\r
+ * the system is halted.\r
+ */\r
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \\r
+ /* System halt code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Trace hook.\r
+ * @details This hook is invoked each time a new record is written in the\r
+ * trace buffer.\r
+ */\r
+#define CH_CFG_TRACE_HOOK(tep) { \\r
+ /* Trace code here.*/ \\r
+}\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/* Port-specific settings (override port settings defaulted in chcore.h). */\r
+/*===========================================================================*/\r
+\r
+#endif /* CHCONF_H */\r
+\r
+/** @} */\r
--- /dev/null
+/*
+Copyright 2015 Jun Wako <wakojun@gmail.com>
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef CONFIG_H
+#define CONFIG_H
+
+
+/* USB Device descriptor parameter */
+#define VENDOR_ID 0xFEED
+#define PRODUCT_ID 0x1111
+#define DEVICE_VER 0x0001
+/* in python2: list(u"whatever".encode('utf-16-le')) */
+/* at most 32 characters or the ugly hack in usb_main.c borks */
+#define MANUFACTURER "TMK"
+#define USBSTR_MANUFACTURER 'T', '\x00', 'M', '\x00', 'K', '\x00', ' ', '\x00'
+#define PRODUCT "ChibiOS TMK test"
+#define USBSTR_PRODUCT 'C', '\x00', 'h', '\x00', 'i', '\x00', 'b', '\x00', 'i', '\x00', 'O', '\x00', 'S', '\x00', ' ', '\x00', 'T', '\x00', 'M', '\x00', 'K', '\x00', ' ', '\x00', 't', '\x00', 'e', '\x00', 's', '\x00', 't', '\x00'
+#define DESCRIPTION "TMK keyboard firmware over ChibiOS"
+
+/* key matrix size */
+#define MATRIX_ROWS 5
+#define MATRIX_COLS 14
+
+/* define if matrix has ghost */
+//#define MATRIX_HAS_GHOST
+
+/* Set 0 if debouncing isn't needed */
+#define DEBOUNCE 5
+
+/* Mechanical locking support. Use KC_LCAP, KC_LNUM or KC_LSCR instead in keymap */
+#define LOCKING_SUPPORT_ENABLE
+/* Locking resynchronize hack */
+#define LOCKING_RESYNC_ENABLE
+
+/* key combination for command */
+#define IS_COMMAND() ( \
+ keyboard_report->mods == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT)) \
+)
+
+
+
+/*
+ * Feature disable options
+ * These options are also useful to firmware size reduction.
+ */
+
+/* disable debug print */
+//#define NO_DEBUG
+
+/* disable print */
+//#define NO_PRINT
+
+/* disable action features */
+//#define NO_ACTION_LAYER
+//#define NO_ACTION_TAPPING
+//#define NO_ACTION_ONESHOT
+//#define NO_ACTION_MACRO
+//#define NO_ACTION_FUNCTION
+
+// TODO: add this to ChibiOS-Contrib/os/common/ext/CMSIS/KINETIS/kl27zxxx.h
+#ifndef USBx_CTL_RESUME
+#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */
+#endif
+
+
+#endif
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/**\r
+ * @file templates/halconf.h\r
+ * @brief HAL configuration header.\r
+ * @details HAL configuration file, this file allows to enable or disable the\r
+ * various device drivers from your application. You may also use\r
+ * this file in order to override the device drivers default settings.\r
+ *\r
+ * @addtogroup HAL_CONF\r
+ * @{\r
+ */\r
+\r
+#ifndef _HALCONF_H_\r
+#define _HALCONF_H_\r
+\r
+#include "mcuconf.h"\r
+\r
+/**\r
+ * @brief Enables the PAL subsystem.\r
+ */\r
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)\r
+#define HAL_USE_PAL TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the ADC subsystem.\r
+ */\r
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)\r
+#define HAL_USE_ADC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the CAN subsystem.\r
+ */\r
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)\r
+#define HAL_USE_CAN FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the DAC subsystem.\r
+ */\r
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)\r
+#define HAL_USE_DAC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the EXT subsystem.\r
+ */\r
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)\r
+#define HAL_USE_EXT FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the GPT subsystem.\r
+ */\r
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)\r
+#define HAL_USE_GPT FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the I2C subsystem.\r
+ */\r
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)\r
+#define HAL_USE_I2C FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the I2S subsystem.\r
+ */\r
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)\r
+#define HAL_USE_I2S FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the ICU subsystem.\r
+ */\r
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)\r
+#define HAL_USE_ICU FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the MAC subsystem.\r
+ */\r
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)\r
+#define HAL_USE_MAC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the MMC_SPI subsystem.\r
+ */\r
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)\r
+#define HAL_USE_MMC_SPI FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the PWM subsystem.\r
+ */\r
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)\r
+#define HAL_USE_PWM FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the RTC subsystem.\r
+ */\r
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)\r
+#define HAL_USE_RTC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SDC subsystem.\r
+ */\r
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)\r
+#define HAL_USE_SDC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SERIAL subsystem.\r
+ */\r
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)\r
+#define HAL_USE_SERIAL FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SERIAL over USB subsystem.\r
+ */\r
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)\r
+#define HAL_USE_SERIAL_USB FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SPI subsystem.\r
+ */\r
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)\r
+#define HAL_USE_SPI FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the UART subsystem.\r
+ */\r
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)\r
+#define HAL_USE_UART FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the USB subsystem.\r
+ */\r
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)\r
+#define HAL_USE_USB TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the WDG subsystem.\r
+ */\r
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)\r
+#define HAL_USE_WDG FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* USB driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)\r
+#define USB_USE_WAIT TRUE\r
+#endif\r
+\r
+#endif /* _HALCONF_H_ */\r
+\r
+/** @} */\r
--- /dev/null
+/*
+Copyright 2012 Jun Wako <wakojun@gmail.com>
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/*
+ * scan matrix
+ */
+#include "print.h"
+#include "debug.h"
+#include "util.h"
+#include "wait.h"
+#include "matrix.h"
+#include "led.h"
+#include "keymap.h"
+#include "timer.h"
+
+
+/* Matrix
+ * COL: input with pullup to sense
+ * PTD6 PTD5 PTD4 PTD3 PTA19 PTA18 PTA4 PTA2 PTA1 PTE25 PTE24 PTE30 PTE29 PTE21
+ *
+ * ROW: output low to strobe
+ * PTB3 PTB16 PTB17 PTC0 PTC1
+ *
+ * State(1:on, 0:off)
+ */
+static matrix_row_t matrix[MATRIX_ROWS];
+static matrix_row_t matrix_debouncing[MATRIX_ROWS];
+static bool debouncing = false;
+static uint16_t debouncing_time = 0;
+
+
+inline
+uint8_t matrix_rows(void)
+{
+ return MATRIX_ROWS;
+}
+
+inline
+uint8_t matrix_cols(void)
+{
+ return MATRIX_COLS;
+}
+
+void matrix_init(void)
+{
+ debug_matrix = true;
+ memset(matrix, 0, MATRIX_ROWS);
+ memset(matrix_debouncing, 0, MATRIX_ROWS);
+
+ // COL: internal pull-up
+ palSetPadMode(GPIOD, 6, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOD, 5, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOD, 4, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOD, 3, PAL_MODE_INPUT_PULLUP);
+
+ palSetPadMode(GPIOA, 19, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOA, 18, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOA, 2, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOA, 1, PAL_MODE_INPUT_PULLUP);
+
+ palSetPadMode(GPIOE, 25, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOE, 24, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOE, 30, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOE, 29, PAL_MODE_INPUT_PULLUP);
+ palSetPadMode(GPIOE, 21, PAL_MODE_INPUT_PULLUP);
+
+ // ROW: Output high
+ palSetPadMode(GPIOB, 3, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetPadMode(GPIOB, 16, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetPadMode(GPIOB, 17, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetPadMode(GPIOC, 0, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetPadMode(GPIOC, 1, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetPad(GPIOB, 3);
+ palSetPad(GPIOB, 16);
+ palSetPad(GPIOB, 17);
+ palSetPad(GPIOC, 0);
+ palSetPad(GPIOC, 1);
+
+
+ // LED blink
+ palSetPadMode(GPIOD, 7, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetPad(GPIOD, 7);
+ chThdSleepMilliseconds(200);
+ palClearPad(GPIOD, 7);
+ chThdSleepMilliseconds(200);
+ palSetPad(GPIOD, 7);
+ chThdSleepMilliseconds(200);
+ palClearPad(GPIOD, 7);
+}
+
+uint8_t matrix_scan(void)
+{
+ for (int row = 0; row < MATRIX_ROWS; row++) {
+ matrix_row_t data = 0;
+
+ // strobe row
+ switch (row) {
+ case 0: palClearPad(GPIOB, 3); break;
+ case 1: palClearPad(GPIOB, 16); break;
+ case 2: palClearPad(GPIOB, 17); break;
+ case 3: palClearPad(GPIOC, 0); break;
+ case 4: palClearPad(GPIOC, 1); break;
+ }
+
+ //wait_us(1);
+ //chThdSleepMicroseconds(1); // TODO: sleep around 1ms for some reason
+ //chThdSleepMilliseconds(1); // seems to work correctly
+
+ data = (!palReadPad(GPIOD, 6) << 0UL) |
+ (!palReadPad(GPIOD, 5) << 1UL) |
+ (!palReadPad(GPIOD, 4) << 2UL) |
+ (!palReadPad(GPIOD, 3) << 3UL) |
+ (!palReadPad(GPIOA, 19) << 4UL) |
+ (!palReadPad(GPIOA, 18) << 5UL) |
+ (!palReadPad(GPIOA, 4) << 6UL) |
+ (!palReadPad(GPIOA, 2) << 7UL) |
+ (!palReadPad(GPIOA, 1) << 8UL) |
+ (!palReadPad(GPIOE, 25) << 9UL) |
+ (!palReadPad(GPIOE, 24) << 10UL) |
+ (!palReadPad(GPIOE, 30) << 11UL) |
+ (!palReadPad(GPIOE, 29) << 12UL) |
+ (!palReadPad(GPIOE, 21) << 13UL);
+
+ // unstrobe row
+ switch (row) {
+ case 0: palSetPad(GPIOB, 3); break;
+ case 1: palSetPad(GPIOB, 16); break;
+ case 2: palSetPad(GPIOB, 17); break;
+ case 3: palSetPad(GPIOC, 0); break;
+ case 4: palSetPad(GPIOC, 1); break;
+ }
+
+ if (matrix_debouncing[row] != data) {
+ matrix_debouncing[row] = data;
+ debouncing = true;
+ debouncing_time = timer_read();
+ }
+ }
+
+ if (debouncing && timer_elapsed(debouncing_time) > DEBOUNCE) {
+ for (int row = 0; row < MATRIX_ROWS; row++) {
+ matrix[row] = matrix_debouncing[row];
+ }
+ debouncing = false;
+ }
+ return 1;
+}
+
+inline
+bool matrix_is_on(uint8_t row, uint8_t col)
+{
+ return (matrix[row] & (1<<col));
+}
+
+inline
+matrix_row_t matrix_get_row(uint8_t row)
+{
+ return matrix[row];
+}
+
+void matrix_print(void)
+{
+ return;
+ xprintf("\nr/c 0123456789ABCDEF\n");
+ for (uint8_t row = 0; row < MATRIX_ROWS; row++) {
+ xprintf("%02X: ", row);
+ matrix_row_t data = matrix_get_row(row);
+ for (int col = 0; col < MATRIX_COLS; col++) {
+ if (data & (1<<col))
+ xprintf("1");
+ else
+ xprintf("0");
+ }
+ xprintf("\n");
+ }
+}
+
+
+//
+// LED
+//
+void led_set(uint8_t usb_led) {
+ if (usb_led & (1<<USB_LED_CAPS_LOCK)) {
+ // output high
+ palSetPadMode(GPIOD, 7, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetPad(GPIOD, 7);
+ } else {
+ // Hi-Z
+ palSetPadMode(GPIOD, 7, PAL_MODE_INPUT);
+ }
+}
+
+
+//
+// Keymap
+//
+const uint8_t keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
+ [0] = {
+ { KC_ESC, KC_1, KC_2, KC_3, KC_4, KC_5, KC_6, KC_7, KC_8, KC_9, KC_0, KC_MINS, KC_EQL, KC_BSLS },
+ { KC_TAB, KC_Q, KC_W, KC_E, KC_R, KC_T, KC_Y, KC_U, KC_I, KC_O, KC_P, KC_LBRC, KC_RBRC, KC_BSPC },
+ { KC_LCTL, KC_A, KC_S, KC_D, KC_F, KC_G, KC_H, KC_J, KC_K, KC_L, KC_SCLN, KC_QUOT, KC_ENT, KC_NO },
+ { KC_LSFT, KC_Z, KC_X, KC_C, KC_V, KC_B, KC_N, KC_M, KC_COMM, KC_DOT, KC_SLSH, KC_RSFT, KC_NO, KC_FN0 },
+ { KC_LCTL, KC_LGUI, KC_LALT, KC_NO, KC_SPC, KC_NO, KC_NO, KC_NO, KC_NLCK, KC_CAPS, KC_MENU, KC_RALT, KC_RGUI, KC_RCTL },
+ },
+ [1] = {
+ { KC_ESC, KC_F1, KC_F2, KC_F3, KC_F4, KC_F5, KC_F6, KC_F7, KC_F8, KC_F9, KC_F10, KC_F11, KC_F12, KC_DEL },
+ { KC_CAPS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_PSCR, KC_SLCK, KC_PAUS, KC_UP, KC_INS, KC_TRNS },
+ { KC_TRNS, KC_VOLD, KC_VOLU, KC_MUTE, KC_TRNS, KC_TRNS, KC_PAST, KC_PSLS, KC_HOME, KC_PGUP, KC_LEFT, KC_RGHT, KC_PENT, KC_TRNS },
+ { KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_PPLS, KC_PMNS, KC_END, KC_PGDN, KC_DOWN, KC_TRNS, KC_TRNS, KC_TRNS },
+ { KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS },
+ },
+};
+
+const action_t fn_actions[] = {
+ [0] = ACTION_LAYER_TAP_KEY(1, KC_GRV),
+};
--- /dev/null
+/*\r
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+#ifndef _MCUCONF_H_\r
+#define _MCUCONF_H_\r
+\r
+#define KL2x_MCUCONF\r
+\r
+/*\r
+ * HAL driver system settings.\r
+ */\r
+#if 1\r
+/* High-frequency internal RC, 48MHz, possible USB clock recovery */\r
+#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_HIRC\r
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL\r
+#define KINETIS_CLKDIV1_OUTDIV1 1\r
+#endif\r
+\r
+#if 0\r
+/* Low-frequency internal RC, 8 MHz mode */\r
+#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_LIRC8M\r
+#define KINETIS_SYSCLK_FREQUENCY 8000000UL\r
+#define KINETIS_CLKDIV1_OUTDIV1 1\r
+#endif\r
+\r
+/*\r
+ * SERIAL driver system settings.\r
+ */\r
+#define KINETIS_SERIAL_USE_UART0 TRUE\r
+\r
+/*\r
+ * USB driver settings\r
+ */\r
+#define KINETIS_USB_USE_USB0 TRUE\r
+/* need to redefine this, since the default is for K20x */\r
+#define KINETIS_USB_USB0_IRQ_PRIORITY 2\r
+\r
+/*\r
+ * Kinetis FOPT configuration byte\r
+ */\r
+/* for KL27: */\r
+#define KINETIS_NV_FOPT_BYTE 0x39\r
+#define KINETIS_NV_FSEC_BYTE 0x7E\r
+/* NV_FOPT: bit7-6/BOOTSRC_SEL=0b00 (11=from ROM; 00=from FLASH)\r
+ bit5/FAST_INIT=1, bit4/LPBOOT1=1,\r
+ bit3/RESET_PIN_CFG=1, bit2/NMI_DIS=1,\r
+ bit1/BOOTPIN_OPT=0, bit0/LPBOOT0=1 */\r
+/* BOOTPIN_OPT: 1=boot depends on BOOTSRC_SEL\r
+ 0=boot samples BOOTCFG0=NMI pin */\r
+/* Boot sequence, page 88 of manual:\r
+ * - If the NMI/BOOTCFG0 input is high or the NMI function is disabled in FTFA_FOPT, the CPU begins execution at the PC location.\r
+ * - If the NMI/BOOTCFG0 input is low, the NMI function is enabled in FTFA_FOPT, and FTFA_FOPT[BOOTPIN_OPT] = 1, this results in an NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler.\r
+ * - When FTFA_FOPT[BOOTPIN_OPT] = 0, it forces boot from ROM if NMI/BOOTCFG0 pin set to 0.\r
+ *\r
+ * Observed behaviour:\r
+ * - when BOOTPIN_OPT=0, BOOTSRC_SEL still matters:\r
+ * - if 0b11 (from ROM), it still boots from ROM, even if BOOTCFG0 pin\r
+ * is high/floating, but leaves ROM and runs user app after\r
+ * 5 seconds delay.\r
+ * - if 0b00 (from FLASH), reset/powerup jumps to user app unless\r
+ * BOOTCFG0 pin is asserted.\r
+ * - in any case, reset when in bootloader induces the 5 second delay\r
+ * before starting the user app.\r
+ * \r
+ */\r
+\r
+#endif /* _MCUCONF_H_ */\r
projects / max / tmk_keyboard.git / commitdiff